LexDanaLexDanabeta
Inventor

Seungyoon Peter Song

Inventor
Austin, TX, US

Overview

53→
Patents
1993–2021
Patent span
Physics
Primary field (CPC G)

Patents· 53 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing65%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use20%
H03KPulse technique7%
G09FDisplaying1%
G09GArrangements or circuits for control of indicating devices using static means to present variable information1%
G11CStatic stores1%
H01LSemiconductor devices1%
H10KOrganic electric solid-state devices1%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution1%
PatentTitleYear
11,107,416Display device202110,740,260Cache self-clean engine202010,705,987Autonomous prefetch engine202010,515,030Method and device for improved advanced microcontroller bus architecture (AMBA) and advanced extensible interface (AXI) operations20198,543,843'Virtual core management'20138,281,308'Virtual core remapping based on temperature'20128,225,315'Virtual core management'20128,219,788'Virtual core management'20127,958,312'Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state'20117,904,659'Power conservation via DRAM access reduction'20117,899,990'Power conservation via DRAM access'20117,802,073'Virtual core management'20107,797,512'Virtual core management'20107,788,473'Prediction of data values read from memory by a microprocessor using the storage destination of a load operation'20107,673,122'Software hint to specify the preferred branch prediction to use for a branch instruction'20107,631,207'Reducing power consumption for processing of common values in microprocessor registers and execution units'20097,587,585'Flag management in processors enabled for speculative execution of micro-operation traces'20097,568,089'Flag management in processors enabled for speculative execution of micro-operation traces'20097,568,088'Flag management in processors enabled for speculative execution of micro-operation traces'20097,533,242'Prefetch hardware efficiency via prefetch hint instructions'20097,516,274'Power conservation via DRAM access reduction'20097,412,570'Small and power-efficient cache that can provide data for background DNA devices while the processor is in a low-power state'20087,389,403'Adaptive computing ensemble microprocessor architecture'20086,957,323'Operand file using pointers and reference counters and a method of use'20056,894,534'Dynamic programmable logic array that can be reprogrammed and a method of use'20056,848,025'Method and system for programmable replacement mechanism for caching devices'20056,614,258'Field-programmable dynamic logic array'20036,542,958'Software control of DRAM refresh to reduce power consumption in a data processing system'20036,502,202'Self-adjusting multi-speed pipeline'20026,433,581'Configurable dynamic programmable logic array'20026,348,812'Dynamic programmable logic array that can be reprogrammed and a method of use'20026,304,102'Repairable dynamic programmable logic array'20016,094,705'Method and system for selective DRAM refresh to reduce power consumption'20006,061,711'Efficient context saving and restoring in a multi-tasking computing system environment'20006,041,167'Method and system for reordering instructions after dispatch in a processing system'20005,991,531'Scalable width vector processor architecture for efficient emulation'19995,922,066'Multifunction data aligner in wide data width processor'19995,893,930'Predictive translation of a data address utilizing sets of associative entries stored consecutively in a translation lookaside buffer'19995,881,307'Deferred store data read with simple anti-dependency pipeline inter-lock control in superscalar processor'19995,838,984'Single-instruction-multiple-data processing using multiple banks of vector registers'19985,805,877'Data processor with branch target address cache and method of operation'19985,799,163'Opportunistic operand forwarding to minimize register file read ports'19985,761,723'Data processor with branch prediction and method of operation'19985,742,802'Method and system for efficiently mapping guest instruction in an emulation assist unit'19985,664,215'Data processor with an execution unit for performing load instructions and method of operation'19975,644,779'Processing system and method of operation for concurrent processing of branch instructions with cancelling of processing of a branch instruction'19975,559,976'System for instruction completion independent of result write-back responsive to both exception free completion of execution and completion of all logically prior instructions'19965,548,738'System and method for processing an instruction in a processing system'19965,546,599'Processing system and method of operation for processing dispatched instructions with detected exceptions'19965,524,224'System for speculatively executing instructions wherein mispredicted instruction is executed prior to completion of branch processing'19965,321,825'Processing system with lock spaces for providing critical section access'19945,289,588'Interlock acquisition for critical code section execution in a shared memory common-bus individually cached multiprocessor system'19945,237,694'Processing system and method including lock buffer for controlling exclusive critical problem accesses by each processor'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2000Based in Austin, TX, US· patent location history
1996–2000Patents assigned to IBM (9)· patent assignee history
1998–1999Patents assigned to SAMSUNG ELECTRONICS CO LTD (5)· patent assignee history
1998–2000Based in Los Altos, CA, US· patent location history
2000–2003Based in Palo Alto, CA, US· patent location history
2001–2005Patents assigned to ELAN RES (7)· patent assignee history
2003–2011Based in East Palo Alto, CA, US· patent location history
2008–2013Patents assigned to SUN MICROSYSTEMS INC (10)· patent assignee history
2009–2020Based in Santa Clara, CA, US· patent location history
2010–2012Patents assigned to ORACLE AMERICA INC (9)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SUN MICROSYSTEMS INC102008–2013
IBM91996–2000
ORACLE AMERICA INC92010–2012
ELAN RES72001–2005
SAMSUNG ELECTRONICS CO LTD51998–1999
Locations
LocationPatentsSpan
Austin, Texas, US121993–2000
East Palo Alto, California, US112003–2011
Santa Clara, California, US102009–2020
Los Altos, California, US81998–2000
Palo Alto, California, US62000–2003