LexDanaLexDanabeta
Inventor

Rajeev Joshi

Inventor
Cupertino, CA, US

Overview

79→
Patents
1997–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 79 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1055%
H05KPrinted circuits8%
B23KSoldering or unsoldering6%
H01LSemiconductor devices6%
Y10TTechnical subjects covered by former us classification6%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
A61NElectrotherapy2%
H10DInorganic electric semiconductor devices2%
H01FMagnets1%
PatentTitleYear
11,032,075Methods for secure cryptogram generation202110,734,313Integration of a passive component in an integrated circuit package202010,714,412Semiconductor package with integrated passive electrical component202010,573,585Power converter having a conductive clip202010,573,582Semiconductor systems having dual leadframes202010,312,184Semiconductor systems having premolded dual leadframes20199,468,087'Power module with improved cooling and method for making'20169,355,946'Converter having partially thinned leadframe with stacked chips and interposer, free of wires and clips'20169,159,656'Semiconductor die package and method for making the same'20159,136,256'Converter having partially thinned leadframe with stacked chips and interposer, free of wires and clips'20159,053,853'Method of forming a magnetics package'20158,679,896'DC/DC converter power module package incorporating a stacked controller and construction methodology'20148,664,752'Semiconductor die package and method for making the same'20148,609,978'Leadframe based photo voltaic electronic assembly'20138,541,890'Substrate based unmolded package'20138,524,532'Integrated circuit package including an embedded power stage wherein a first field effect transistor (FET) and a second FET are electrically coupled therein'20138,339,231'Leadframe based magnetics package'20128,278,742'Thermal enhanced upper and dual heat sink exposed molded leadless package and method'20128,212,361'Semiconductor die package including multiple dies and a common node structure'20128,183,088'Semiconductor die package and method for making the same'20127,971,350'Method of providing a RF shield of an electronic device'20117,968,982'Thermal enhanced upper and dual heat sink exposed molded leadless package'20117,932,171'Dual metal stud bumping for flip chip applications'20117,892,884'High performance multi-chip flip chip package'20117,842,555'Integrated transistor module and method of fabricating same'20107,821,124'Thin, thermally enhanced flip chip in a leaded molded package'20107,790,513'Substrate based unmolded package'20107,772,681'Semiconductor die package and method for making the same'20107,682,877'Substrate based unmolded package'20107,632,719'Wafer-level chip scale package and method for fabricating and using the same'20097,618,896'Semiconductor die package including multiple dies and a common node structure'20097,582,956'Flip chip in leaded molded package and method of manufacture thereof'20097,537,958'High performance multi-chip flip chip package'20097,525,179'Lead frame structure with aperture or groove for flip chip in a leaded molded package'20097,504,281'Substrate based unmolded package'20097,501,337'Dual metal stud bumping for flip chip applications'20097,501,702'Integrated transistor module and method of fabricating same'20097,468,548'Thermal enhanced upper and dual heat sink exposed molded leadless package'20087,439,613'Substrate based unmolded package'20087,393,718'Unmolded package for a semiconductor device'20087,335,532'Method of assembly for multi-flip chip on lead frame on overmolded IC package'20087,332,806'Thin, thermally enhanced molded package with leadframe having protruding region'20087,315,077'Molded leadless package having a partially exposed lead frame pad'20087,271,497'Dual metal stud bumping for flip chip applications'20077,256,479'Method to manufacture a universal footprint for a package with exposed chip'20077,215,011'Flip chip in leaded molded package and method of manufacture thereof'20077,196,313'Surface mount multi-channel optocoupler'20077,154,186'Multi-flip chip on lead frame on over molded IC package and method of assembly'20067,154,168'Flip chip in leaded molded package and method of manufacture thereof'20067,101,734'Flip chip substrate design'20067,081,666'Lead frame structure with aperture or groove for flip chip in a leaded molded package'20067,061,077'Substrate based unmolded package including lead frame structure and semiconductor die'20067,029,947'Flip chip in leaded molded package with two dies'20067,022,548'Method for making a semiconductor die package'20067,008,868'Passivation scheme for bumped wafers'20066,992,384'High performance multi-chip flip chip package'20066,953,998'Unmolded package for a semiconductor device'20056,949,410'Flip chip in leaded molded package and method of manufacture thereof'20056,891,256'Thin, thermally enhanced flip chip in a leaded molded package'20056,867,481'Lead frame structure with aperture or groove for flip chip in a leaded molded package'20056,836,023'Structure of integrated trace of chip package'20046,806,580'Multichip module including substrate with an array of interconnect structures'20046,798,044'Flip chip in leaded molded package with two dies'20046,753,605'Passivation scheme for bumped wafers'20046,731,003'Wafer-level coated copper stud bumps'20046,720,642'Flip chip in leaded molded package and method of manufacture thereof'20046,696,321'High performance multi-chip flip chip package'20046,683,375'Semiconductor die including conductive columns'20046,661,082'Flip chip substrate design'20036,633,030'Surface mountable optocoupler package'20036,627,991'High performance multi-chip flip package'20036,566,749'Semiconductor die package with improved thermal and electrical performance'20036,489,678'High performance multi-chip flip chip package'20026,469,384'Unmolded package for a semiconductor device'20026,294,403'High performance flip chip package'20016,133,634'High performance flip chip package'20005,789,809'Thermally enhanced micro-ball grid array package'19985,765,280'Method for making a carrier based IC packaging arrangement'19985,637,916'Carrier based IC packaging arrangement'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2014Patents assigned to NAT SEMICONDUCTOR CORP (4)· patent assignee history
1997–2020Based in Cupertino, CA, US· patent location history
1998Based in Sunnyvale, CA, US· patent location history
2000–2015Patents assigned to FAIRCHILD SEMICONDUCTOR (57)· patent assignee history
2006–2009Based in San Jose, CA, US· patent location history
2011–2015Patents assigned to FLEXTRONICS AP LLC (4)· patent assignee history
2012–2015Patents assigned to JOSHI RAJEEV (8)· patent assignee history
2013–2020Patents assigned to TEXAS INSTRUMENTS INC (9)· patent assignee history
2021Based in San Ramon, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
FAIRCHILD SEMICONDUCTOR572000–2015
TEXAS INSTRUMENTS INC92013–2020
JOSHI RAJEEVself82012–2015
FLEXTRONICS AP LLC42011–2015
NAT SEMICONDUCTOR CORP41997–2014
Locations
LocationPatentsSpan
Cupertino, California, US751997–2020
San Jose, California, US22006–2009
San Ramon, California, US12021
Sunnyvale, California, US11998