Inventor
Berthold Reimer
Inventor
Dresden, DE
Overview
Patents· 15 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices37%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1031%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
H01LSemiconductor devices14%
PatentTitleYear
10,559,593Field-effect transistors with a grown silicon-germanium channel20209,842,762'Method of manufacturing a semiconductor wafer having an SOI configuration'20179,054,041'Methods for etching dielectric materials in the fabrication of integrated circuits'20158,951,901'Superior integrity of a high-K gate stack by forming a controlled undercut on the basis of a wet chemistry'20158,815,674'Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions'20148,716,136'Method of forming a semiconductor structure including a wet etch process for removing silicon nitride'20148,703,620'Methods for PFET fabrication using APM solutions'20148,658,543'Methods for pFET fabrication using APM solutions'20148,580,133'Methods of controlling the etching of silicon nitride relative to silicon dioxide'20138,524,591'Maintaining integrity of a high-K gate stack by passivation using an oxygen plasma'20138,445,344'Uniform high-k metal gate stacks by adjusting threshold voltage for sophisticated transistors by diffusing a metal species prior to gate patterning'20138,357,575'Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers'20138,283,232'Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing'20128,247,281'Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers'20128,048,748'Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor device'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011–2020Patents assigned to GLOBALFOUNDRIES INC (15)· patent assignee history
2011–2020Based in Dresden, DE· patent location history
2012–2015Patents assigned to REIMER BERTHOLD (9)· patent assignee history
2012–2015Patents assigned to BEYER SVEN (4)· patent assignee history
2012–2015Patents assigned to GRAETSCH FALK (3)· patent assignee history
2012–2013Patents assigned to GROSCHOPF JOHANNES (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES INC | 15 | 2011–2020 |
| REIMER BERTHOLDself | 9 | 2012–2015 |
| BEYER SVEN | 4 | 2012–2015 |
| GRAETSCH FALK | 3 | 2012–2015 |
| GROSCHOPF JOHANNES | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Dresden, DE | 15 | 2011–2020 |