Inventor
David B. Kramer
Inventor
Cedar Park, TX, US
Overview
Patents· 42 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing40%
H04LTransmission of digital information, e.g. telegraphic communication34%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes12%
H04QSelecting4%
E05BLocks2%
E05CBolts or fastening devices for wings, specially for doors or windows2%
H05KPrinted circuits2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
Y10TTechnical subjects covered by former us classification2%
PatentTitleYear
10,241,683Non-volatile RAM system20199,733,981'System and method for conditional task switching during ordering scope transitions'20179,501,442'Configurable peripheral componenent interconnect express (PCIe) controller'20169,442,870'Interrupt priority management using partition-based priority blocking processor registers'20169,436,626'Processor interrupt interface with interrupt partitioning and virtualization enhancements'20169,330,054'System and method for assigning a message'20169,229,884'Virtualized instruction extensions for system partitioning'20169,207,979'Explicit barrier scheduling mechanism for pipelining of stream processing algorithms'20159,195,621'System and method for assigning memory access transfers between communication channels'20159,152,587'Virtualized interrupt delay mechanism'20159,128,925'System and method for direct memory access buffer utilization by setting DMA controller with plurality of arbitration weights associated with different DMA engines'20159,054,998'System and method for maintaining packet order in an ordered data stream'20158,959,278'System and method for scalable movement and replication of data'20158,924,784'Controller for managing a reset of a subset of threads in a multi-thread system'20148,914,550'System and method for transferring data between components of a data processor'20148,638,800'Technique for generating hash-tuple independent of precedence order of applied rules'20148,615,614'Message passing using direct memory access unit in a data processing system'20138,572,322'Asynchronously scheduling memory access requests'20138,566,179'Mortgage and real estate data integration and presentation system'20138,560,796'Scheduling memory access requests using predicted memory timing and state information'20138,560,782'Method and apparatus for determining access permissions in a partitioned data processing system'20138,473,372'Mortgage and real estate data integration and presentation system'20138,447,897'Bandwidth control for a direct memory access unit within a data processing system'20138,315,911'Mortgage and real estate data integration and presentation system'20128,280,778'Mortgage and real estate data integration and presentation system'20128,214,259'Mortgage and real estate data integration and presentation system'20128,209,232'Mortgage and real estate data integration and presentation system'20127,912,069'Virtual segmentation system and method of operation thereof'20117,894,440'Programmable hash-tuple generation with parallel rule implementation independence'20117,861,291'System and method for implementing ACLs using standard LPM engine'20107,850,013'Locking mechanism for rack mounted devices'20107,477,636'Processor with scheduler architecture supporting multiple distinct scheduling algorithms'20097,443,793'Processor with dynamic table-based scheduling using linked transmission elements for handling transmission request collisions'20087,411,972'Link layer device with non-linear polling of multiple physical layer device ports'20087,245,624'Processor with table-based scheduling using software-controlled interval computation'20077,224,681'Processor with dynamic table-based scheduling using multi-entry table locations for handling transmission request collisions'20077,215,675'Processor with software-controlled programmable service levels'20077,159,061'Link layer device with configurable address pin allocation'20077,149,211'Virtual reassembly system and method of operation thereof'20067,116,680'Processor architecture and a method of processing'20067,009,979'Virtual segmentation system and method of operation thereof'20066,850,516'Virtual reassembly system and method of operation thereof'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2011Patents assigned to AGERE SYSTEMS INC (12)· patent assignee history
2005–2011Based in Austin, TX, US· patent location history
2010–2019Patents assigned to FREESCALE SEMICONDUCTOR INC (22)· patent assignee history
2010–2019Based in Cedar Park, TX, US· patent location history
2010Based in San Jose, CA, US· patent location history
2012–2013Based in Wylie, TX, US· patent location history
2013–2017Patents assigned to KRAMER DAVID B (18)· patent assignee history
2013–2017Patents assigned to XU KUN (11)· patent assignee history
2013–2017Patents assigned to JOKINEN TOMMI M (8)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FREESCALE SEMICONDUCTOR INC | 22 | 2010–2019 |
| KRAMER DAVID Bself | 18 | 2013–2017 |
| AGERE SYSTEMS INC | 12 | 2005–2011 |
| XU KUN | 11 | 2013–2017 |
| JOKINEN TOMMI M | 8 | 2013–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cedar Park, Texas, US | 23 | 2010–2019 |
| Austin, Texas, US | 12 | 2005–2011 |
| Wylie, Texas, US | 6 | 2012–2013 |
| San Jose, California, US | 1 | 2010 |