Inventor
DEAN D. GANS
Inventor
US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores37%
G06FElectric digital data processing32%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use15%
H03KPulse technique5%
H04LTransmission of digital information, e.g. telegraphic communication4%
H04BTransmission3%
H01LSemiconductor devices2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
12,587,418Multiplexing distinct signals on a single pin of a memory device202612,573,443Apparatuses and methods for a multi-bit duty cycle monitor202612,517,828Variable modulation scheme for memory device access or operation202612,468,589Methods for activity-based memory maintenance operations and memory devices and systems employing the same202512,423,010Memory devices with multiple sets of latencies and methods for operating the same202512,347,521Time delay indication for host in memory system202512,314,575Memory system and operations of the same202512,308,090Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters202512,265,489Communicating data with stacked memory dies202512,223,998Apparatuses and methods for input receiver circuits and receiver masks for same202512,182,397Apparatuses and methods for configurable memory array bank architectures202412,183,383Methods for row hammer mitigation and memory devices and systems employing the same202412,159,660Methods for row hammer mitigation and memory devices and systems employing the same202412,001,715Memory with virtual page size202411,971,820Variable modulation scheme for memory device access or operation202411,955,162Apparatuses and methods for input receiver circuits and receiver masks for same202411,955,977Apparatuses and methods for duty cycle adjustment of a semiconductor device202411,947,412Methods for activity-based memory maintenance operations and memory devices and systems employing the same202411,914,874Memory devices with multiple sets of latencies and methods for operating the same202411,915,788Indication in memory system or sub-system of latency associated with performing an access command202411,907,546Memory system and operations of the same202411,901,037Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters202411,894,044Apparatuses and methods for a multi-bit duty cycle monitor202411,837,272Methods for row hammer mitigation and memory devices and systems employing the same202311,822,477Prefetch management for memory202311,810,610Methods for row hammer mitigation and memory devices and systems employing the same202311,775,460Communicating data with stacked memory dies202311,698,726Apparatuses and methods for configurable memory array bank architectures202311,682,447Apparatuses and methods for input receiver circuits and receiver masks for same202311,610,613Multiple concurrent modulation schemes in a memory system202311,604,606Prefetch signaling in memory system or subsystem202311,599,474Stacked memory dice for combined access operations202311,568,906Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters202311,550,650Methods for activity-based memory maintenance operations and memory devices and systems employing the same202311,429,291Memory system and operations of the same202211,403,241Communicating data with stacked memory dies202211,397,679Variable modulation scheme for memory device access or operation202211,381,432Multiplexing distinct signals on a single pin of a memory device202211,355,169Indicating latency associated with a memory request in a system202211,340,830Memory buffer management and bypass202211,209,981Apparatuses and methods for configurable memory array bank architectures202111,210,019Memory with virtual page size202111,194,726Stacked memory dice for combined access operations202111,189,334Apparatuses and methods for a multi-bit duty cycle monitor202111,152,929Apparatuses for duty cycle adjustment of a semiconductor device202111,150,821Memory devices with multiple sets of latencies and methods for operating the same2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to MICRON TECHNOLOGY INC (28)· patent assignee history
2021–2026Based in US· patent location history
2023–2026Patents assigned to LODESTAR LICENSING GROUP LLC (18)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 28 | 2021–2026 |
| LODESTAR LICENSING GROUP LLC | 18 | 2023–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 46 | 2021–2026 |