Inventor
Robert L. Sankman
Inventor
Phoenix, AZ, US
Overview
Patents· 92 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1032%
H01LSemiconductor devices23%
H05KPrinted circuits13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
Y10TTechnical subjects covered by former us classification6%
G02BOptical elements, systems or apparatus2%
H10DInorganic electric semiconductor devices2%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
C09JAdhesives1%
PatentTitleYear
11,127,727Thermal spreading management of 3D stacked integrated circuits202111,114,394Signal routing carrier202111,112,8415G mmWave cooling through PCB202111,114,353Hybrid microelectronic substrates202111,107,780Pseudo-stripline using double solder-resist structure202111,043,457Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same202110,985,080Electronic package that includes lamination layer202110,910,317Semiconductor package having wafer-level active die and external die mount202110,811,366Microelectronic bond pads having integrated spring structures202010,763,215Hybrid microelectronic substrate and methods for fabricating the same202010,716,214Hybrid microelectronic substrate and methods for fabricating the same202010,707,168Embedded multi-die interconnect bridge packages with lithographically formed bumps and methods of assembling same202010,700,051Multi-chip packaging202010,685,947Distributed semiconductor die and package architecture202010,658,279High density package interconnects202010,651,116Planar integrated circuit package interconnects202010,651,051Embedded semiconductive chips in reconstituted wafers, and systems containing same202010,634,594Membrane test for mechanical testing of stretchable electronics202010,576,590Torque controlled driver apparatus and method202010,535,595Conductive base embedded interconnect202010,424,561Integrated circuit structures with recessed conductive contacts for package on package201910,416,378Chip-to-chip interconnect with embedded electro-optical bridge structures201910,396,046Substrate assembly with magnetic feature201910,325,860Microelectronic bond pads having integrated spring structures201910,304,769Multi-die package201910,264,717Electromagnetic interference shields for electronic packages and related methods201910,204,851High density package interconnects201910,163,798Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same201810,163,810Electromagnetic interference shielding for system-in-package technology201810,156,583Method of making an accelerometer201810,128,225Interconnect structures with polymer core201810,090,2773D integrated circuit package with through-mold first level interconnects201810,070,524Method of making glass core substrate for integrated circuit devices201810,056,182Surface-mount inductor structures for forming one or more inductors with substrate traces201810,008,452Microelectronic structures having laminated or embedded glass routing structures for high density packaging201810,002,814Apparatuses and methods to enhance passivation and ILD reliability20189,971,089Chip-to-chip interconnect with embedded electro-optical bridge structures20189,941,054Integration of embedded thin film capacitors in package substrates20189,927,211'Cloaking system with waveguides'20189,922,916'High density package interconnects'20189,918,414'Electromagnetic interference shields for electronic packages and related methods'20189,865,568'Integrated circuit structures with recessed conductive contacts for package on package'20189,847,234Embedded semiconductive chips in reconstituted wafers, and systems containing same20179,820,384'Flexible electronic assembly method'20179,807,866'Shielding mold for electric and magnetic EMI mitigation'20179,741,664'High density substrate interconnect formed through inkjet printing'20179,708,178'Integration of laminate MEMS in BBUL coreless package'20179,686,861'Glass core substrate for integrated circuit devices and methods of making the same'20179,646,851'Embedded semiconductive chips in reconstituted wafers, and systems containing same'20179,642,248'Microelectronic structures having laminated or embedded glass routing structures for high density packaging'20179,613,934'Interconnect structures with polymer core'20179,576,909'Bumpless die-package interface for bumpless build-up layer (BBUL)'20179,543,224'Hybrid exposure for semiconductor devices'20179,530,758'3D integrated circuit package with through-mold first level interconnects'20169,420,693'Integration of embedded thin film capacitors in package substrates'20169,374,162'Semiconductor package with optical port'20169,368,437'High density package interconnects'20169,349,703'Method for making high density substrate interconnect using inkjet printing'20169,310,565'Cloaking system with waveguides'20169,297,824'Techniques, systems and devices related to acceleration measurement'20169,263,329'Methods of connecting a first electronic package to a second electronic package'20169,224,674'Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages'20159,190,388'Using an optically transparent solid material as a support structure for attachment of a semiconductor material to a substrate'20159,177,831'Die assembly on thin dielectric sheet'20159,099,444'3D integrated circuit package with through-mold first level interconnects'20159,001,520'Microelectronic structures having laminated or embedded glass routing structures for high density packaging'20158,987,918'Interconnect structures with polymer core'20158,969,140'Embedded semiconductive chips in reconstituted wafers, and systems containing same'20158,963,135'Integrated circuits and systems and methods for producing the same'20158,535,989'Embedded semiconductive chips in reconstituted wafers, and systems containing same'20138,465,297'Self referencing pin'20138,450,857'Through mold via polymer block package'20138,354,748'In-package microelectronic apparatus, and methods of using same'20138,278,214'Through mold via polymer block package'20128,207,453'Glass core substrate for integrated circuit devices and methods of making the same'20128,110,920'In-package microelectronic apparatus, and methods of using same'20127,932,596'Thermally enhanced electronic flip-chip packaging with external-connector-side die and method'20117,852,189'Packaged spiral inductor structures, processes of making same, and systems containing same'20107,637,008'Methods for manufacturing imprinted substrates'20097,456,047'Thermally enhanced electronic flip-chip packaging with external-connector-side die and method'20087,268,425'Thermally enhanced electronic flip-chip packaging with external-connector-side die and method'20077,239,524'Resistive element apparatus and method'20077,133,294'Integrated circuit packages with sandwiched capacitors'20067,046,528'Load-dependent variable frequency voltage regulator'20066,900,991'Electronic assembly with sandwiched capacitors and methods of manufacture'20056,717,277'Electrical assembly with vertical multiple layer structure'20046,680,218'Fabrication method for vertical electronic circuit package and system'20046,664,483'Electronic package with high density interconnect and associated methods'20036,632,734'Parallel plane substrate'20036,563,210'Parallel plane substrate'20036,555,920'Vertical electronic circuit package'20036,388,207'Electronic assembly with trench structures and methods of manufacture'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2021Patents assigned to INTEL CORP (91)· patent assignee history
2002–2021Based in Phoenix, AZ, US· patent location history
2012–2020Patents assigned to SANKMAN ROBERT L (17)· patent assignee history
2012–2018Patents assigned to MA QING (4)· patent assignee history
2012–2013Patents assigned to DATTAGURU SRIRAM (2)· patent assignee history
2015–2017Patents assigned to TEH WENG HONG (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 91 | 2002–2021 |
| SANKMAN ROBERT Lself | 17 | 2012–2020 |
| MA QING | 4 | 2012–2018 |
| TEH WENG HONG | 3 | 2015–2017 |
| DATTAGURU SRIRAM | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Phoenix, AZ, US | 92 | 2002–2021 |