Inventor
Nicholas G. Samra
Inventor
Austin, TX, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing78%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%
G11CStatic stores4%
H01LSemiconductor devices4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
PatentTitleYear
8,860,199'Multi-die processor'20148,694,976'Sleep state mechanism for virtual multithreading'20148,219,836'Methods and apparatus to monitor instruction types and control power consumption within a processor'20127,669,203'Virtual multithreading translation mechanism including retrofit capability'20107,653,904'System for forming a critical update loop to continuously reload active thread state from a register storing thread state until another active thread is detected'20107,398,372'Fusing load and alu operations'20087,308,563'Dual-target block register allocation'20077,246,219'Methods and apparatus to control functional blocks within a processor'20077,080,236'Updating stack pointer based on instruction bit indicator without executing an update microinstruction'20067,051,190'Intra-instruction fusion'20066,907,518'Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same'20056,889,314'Method and apparatus for fast dependency coordinate matching'20056,581,155'Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same'20036,560,671'Method and apparatus for accelerating exchange or swap instructions using a register alias table (RAT) and content addressable memory (CAM) with logical register numbers as input addresses'20036,519,683'System and method for instruction cache re-ordering'20036,470,435'Dual state rename recovery using register usage'20026,412,063'Multiple-operand instruction in a two operand pipeline and processor employing the same'20026,275,926'System and method for writing back multiple results over a single-result bus and processor employing the same'20015,809,530'Method and apparatus for processing multiple cache misses using reload folding and store merging'19985,765,208'Method of speculatively executing store instructions prior to performing snoop operations'19985,646,878'Content addressable memory system'19975,448,722'Method and system for data processing system error diagnosis utilizing hierarchical blackboard diagnostic sessions'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2014Based in Austin, TX, US· patent location history
1997–1998Patents assigned to MOTOROLA INC (3)· patent assignee history
1998–2002Based in Plano, TX, US· patent location history
2001–2002Patents assigned to VIA CYRIX INC (2)· patent assignee history
2002–2014Patents assigned to INTEL CORP (14)· patent assignee history
2003–2005Patents assigned to NAT SEMICONDUCTOR CORP (2)· patent assignee history
2012–2014Patents assigned to SAMRA NICHOLAS G (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 14 | 2002–2014 |
| MOTOROLA INC | 3 | 1997–1998 |
| SAMRA NICHOLAS Gself | 3 | 2012–2014 |
| NAT SEMICONDUCTOR CORP | 2 | 2003–2005 |
| VIA CYRIX INC | 2 | 2001–2002 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 18 | 1995–2014 |
| Plano, Texas, US | 4 | 1998–2002 |