Inventor
Hung-Hsin Hsu
Inventor
Hsinchu County, TW
Overview
Patents· 41 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1037%
H01LSemiconductor devices28%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
B01FMixing, e.g. dissolving, emulsifying or dispersing3%
G01RMeasuring electric variables2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
B01JChemical or physical processes, e.g. catalysis or colloid chemistry1%
B05BSpraying apparatus1%
B65DContainers for storage or transport of articles or materials, e.g. bags, barrels, bottles, boxes, cans, cartons, crates, drums, jars, tanks, hoppers, forwarding containers1%
B65GTransport or storage devices, e.g. conveyors for loading or tipping, shop conveyor systems or pneumatic tube conveyors1%
PatentTitleYear
10,862,202Integrated antenna package structure and manufacturing method thereof202010,840,200Manufacturing method of chip package structure comprising encapsulant having concave surface202010,796,931Manufacturing method of package structure202010,788,205Atomizing system202010,756,065Method thereof of package structure202010,629,559Semiconductor package and manufacturing method thereof202010,629,554Package structure and manufacturing method thereof202010,593,647Package structure and manufacturing method thereof202010,522,512Semiconductor package and manufacturing method thereof201910,512,890Apparatus for mixing materials which have a high mix proportion/ratio therebetween and preparation production system using the same201910,515,936Package structure and manufacturing method thereof201910,438,931Package structure and manufacturing method thereof201910,424,526Chip package structure and manufacturing method thereof201910,381,278Testing method of packaging process and packaging structure201910,354,978Stacked package including exterior conductive element and a manufacturing method of the same201910,332,844Manufacturing method of package structure201910,300,441Injection mixer201910,276,553Chip package structure and manufacturing method thereof201910,276,526Semiconductor package structure and manufacturing method thereof201910,269,671Package structure and manufacturing method thereof201910,249,585Stackable semiconductor package and manufacturing method thereof201910,224,254Package process method including disposing a die within a recess of a one-piece material201910,177,011Chip packaging method by using a temporary carrier for flattening a multi-layer structure201910,177,060Chip package structure and manufacturing method thereof201910,170,458Manufacturing method of package-on-package structure201910,163,834Chip package structure comprising encapsulant having concave surface201810,157,828Chip package structure with conductive pillar and a manufacturing method thereof201810,141,276Semiconductor package structure and manufacturing method thereof201810,079,218Test method for a redistribution layer201810,002,848Test method for a redistribution layer20189,991,206Package method including forming electrical paths through a mold layer20189,972,554Wafer level chip scale package having continuous through hole via configuration and fabrication method thereof20189,825,005'Semiconductor package with Pillar-Top-Interconnection (PTI) configuration and its MIS fabricating method'20178,237,273'Metal post chip connecting device and method free to use soldering material'20128,212,349'Semiconductor package having chip using copper process'20128,115,319'Flip chip package maintaining alignment during soldering'20128,048,721'Method for filling multi-layer chip-stacked gaps'20117,902,666'Flip chip device having soldered metal posts by surface mounting'20117,879,648'Fabrication method for high pin count chip package'20117,663,204'Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications'20107,605,462'Universal substrate for a semiconductor device having selectively activated fuses'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2020Patents assigned to POWERTECH TECHNOLOGY INC (38)· patent assignee history
2009–2017Based in Hsinchu, TW· patent location history
2012Patents assigned to HSU HUNG-HSIN (3)· patent assignee history
2012Patents assigned to KO CHIH-MING (2)· patent assignee history
2012Patents assigned to HSU CHIN-MING (1)· patent assignee history
2018–2020Based in Hsinchu County, TW· patent location history
2019–2020Patents assigned to ASIA IC MIC PROCESS INC (3)· patent assignee history
2019Based in Taipei, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| POWERTECH TECHNOLOGY INC | 38 | 2009–2020 |
| ASIA IC MIC PROCESS INC | 3 | 2019–2020 |
| HSU HUNG-HSINself | 3 | 2012 |
| KO CHIH-MING | 2 | 2012 |
| HSU CHIN-MING | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu County, TW | 31 | 2018–2020 |
| Hsinchu, TW | 9 | 2009–2017 |
| Taipei, TW | 1 | 2019 |