LexDanaLexDanabeta
Inventor

Chun-Ying Chen

Inventor
Irvine, CA, US

Overview

71→
Patents
2004–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 71 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Mprimary
H03MCoding19%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses8%
G11BInformation storage based on relative movement between record carrier and transducer7%
H04LTransmission of digital information, e.g. telegraphic communication7%
G05FSystems for regulating electric or magnetic variables6%
G06FElectric digital data processing5%
H02JElectric power networks5%
H04BTransmission5%
H03DDemodulation or transference of modulation from one carrier to another5%
H03HImpedance networks, e.g. resonant circuits5%
PatentTitleYear
10,693,484Pipelined analog-to-digital converter calibration202010,637,493Digital calibration of capacitive mismatches in analog-to-digital converters202010,141,960System for and method of reducing transmit signal distortion20189,379,726'Adaptive asynchronous SAR ADC'20169,118,339'Companding M-digital-to-analog converter (DAC) for a pipelined analog-to-digital converter (ADC)'20159,030,344'System and method for integration of hybrid pipeline'20158,878,707'Time-interleaved skew reduced pipelined analog to digital converter'20148,730,073'Pipelined analog-to-digital converter with dedicated clock cycle for quantization'20148,717,209'Successive equalizer for analog-to-digital converter (ADC) error correction'20148,536,614'Nitride semiconductor light emitting device with magnetic film'20138,427,228'System including adaptive power rails and related method'20138,286,013'Portable communication device with multi-tiered power save operation'20128,254,513'Inter-device adaptable interfacing clock skewing'20128,250,499'Integrated circuit with on-board power utilization information'20128,233,578'Phase-interpolator based PLL frequency synthesizer'20128,181,045'Power control bus'20128,179,293'Programmable settling for high speed analog to digital converter'20128,145,921'Multi-regulator power supply chip with common control bus'20128,072,096'Integrated circuit with multiple independent power supply zones'20117,953,459'Low power warning in a portable communication device based on predicted device utilization'20117,928,874'Analog to digital converter with dynamic power configuration'20117,925,906'Multi-voltage multi-battery power management unit'20117,926,008'Integrated circuit with on-board power utilization information'20117,920,366'ESD configuration for low parasitic capacitance I/O'20117,898,314'Offset compensation using non-uniform calibration'20117,843,370'Programmable settling for high speed analog to digital converter'20107,843,368'Programmable settling for high speed analog to digital converter'20107,817,072'Analog to digital converter with dynamic power configuration'20107,812,747'System and method for common mode calibration in an analog to digital converter'20107,783,275'Integrated direct conversion satellite tuner'20107,750,500'Integrated circuit with multiple independent power supply zones'20107,751,516'Inter-device adaptable interfacing clock skewing'20107,746,046'Power management unit for use in portable applications'20107,707,434'Power control bus for carrying power control information indicating a power supply voltage variability'20107,705,463'Biasing device for low parasitic capacitance in integrated circuit applications'20107,696,704'Discharge lamp driving device and electronic device using the same'20107,656,986'Low jitter phase rotator'20107,623,050'Digital calibration loop for an analog to digital converter'20097,557,640'Regulated charge pump with digital resistance control'20097,548,767'Low power warning in a portable communication device based on predicted device utilization'20097,525,366'Offset compensation using non-uniform calibration'20097,509,507'Multi-regulator power supply chip with common control bus'20097,508,272'Methods and systems to provide a plurality of signals having respective different phases'20097,505,238'ESD configuration for low parasitic capacitance I/O'20097,466,249'System and method for common mode calibration in an analog to digital converter'20087,456,764'Analog to digital converter with dynamic power configuration'20087,394,310'System and method for programmable switching characteristics of an analog switch in a transconductance amplifier'20087,391,595'System and method for breakdown protection in start-up sequence with multiple power domains'20087,379,520'Low jitter phase rotator'20087,274,260'Methods and systems to provide a plurality of signals having respective different phases'20077,224,156'Voltage regulator for use in portable applications'20077,209,848'Pulse stretching architecture for phase alignment for high speed data acquisition'20077,162,002'Phase-interpolator based PLL frequency synthesizer'20077,161,339'High voltage power management unit architecture in CMOS process'20077,161,443'Temperature compensated crystal oscillator'20077,142,039'Regulated charge pump with digital resistance control'20067,139,547'Integrated direct conversion satellite tuner'20067,135,730'Bias-independent capacitor based on superposition of nonlinear capacitors for analog/RF circuit applications'20067,126,319'Low leakage CMOS power mux'20067,116,176'Multiple synthesized clocks from a single clock source'20067,091,617'Design and layout techniques for low parasitic capacitance in analog circuit applications'20067,071,652'Methods and systems for battery charging control based on CMOS technology'20067,053,697'System for tuning a corner frequency of a low pass filter'20067,030,790'Systems and methods for auto gain control in Bi-CMOS digital to analog converters'20067,020,210'Inter-device adaptable interfacing clock skewing'20066,949,910'Methods and systems for battery charging control based on CMOS technology'20056,922,109'Multiple synthesized clocks with fractional PPM control from a single clock source'20056,894,557'Method for tuning a corner frequency of a low pass filter'20056,894,472'Low leakage CMOS power mux'20056,879,142'Power management unit for use in portable applications'20056,710,644'Low pass filter corner frequency tuning circuit and method'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2016Patents assigned to BROADCOM CORP (65)· patent assignee history
2004–2020Based in Irvine, CA, US· patent location history
2006Based in Laguna Beach, CA, US· patent location history
2009–2014Patents assigned to CHEN CHUN-YING (12)· patent assignee history
2010Based in Taipei, TW· patent location history
2011–2012Patents assigned to VORENKAMP PIETER (6)· patent assignee history
2011–2012Patents assigned to KIM NEIL Y (5)· patent assignee history
2011–2012Patents assigned to RANGANATHAN SUMANT (5)· patent assignee history
2013Based in Taichung, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
BROADCOM CORP652004–2016
CHEN CHUN-YINGself122009–2014
VORENKAMP PIETER62011–2012
KIM NEIL Y52011–2012
RANGANATHAN SUMANT52011–2012
Locations
LocationPatentsSpan
Irvine, California, US682004–2020
Taichung, TW12013
Taipei, TW12010
Laguna Beach, California, US12006