Inventor
Tung Ying Lee
Inventor
Hsinchu, TW
Overview
Patents· 93 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices30%
H01LSemiconductor devices30%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
B82YSpecific uses or applications of nanostructures5%
H10BElectronic memory devices3%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%
G06TImage data processing or generation, in general1%
H04NPictorial communication, e.g. television1%
H10NElectric solid-state devices not otherwise provided for1%
PatentTitleYear
10,879,130Semiconductor device structure with semiconductor wire202010,872,955Semiconductor device and fabricating method thereof202010,868,004Semiconductor devices having Fin Field Effect Transistor (FinFET) structures and manufacturing and design methods thereof202010,868,009Semiconductor device and manufacturing method thereof202010,867,841Semiconductor device and method of manufacturing the same202010,862,031Method to effectively suppress heat dissipation in PCRAM devices202010,854,749Source/drain structure having multi-facet surfaces202010,847,716Method for manufacturing a phase change memory device having a second opening above a first opening in the dielectric layer202010,825,915Spacers for nanowire-based integrated circuit device and method of fabricating same202010,825,907Self-aligned contact and manufacturing method thereof202010,825,933Gate-all-around structure and manufacturing method for the same202010,825,899Semiconductor device and fabricating method thereof202010,818,777Method of manufacturing a semiconductor device and a semiconductor device202010,811,518Method of manufacturing a semiconductor device and a semiconductor device202010,804,375Semiconductor device and method for manufacturing the same202010,797,174Semiconductor device with fin end spacer dummy gate and method of manufacturing the same202010,770,290Method for forming stacked nanowire transistors202010,727,230Integrated semiconductor device with 2D material layer202010,727,110Semiconductor device and method of manufacturing the same202010,714,592Method of manufacturing a semiconductor device and a semiconductor device202010,714,597FinFETs with low source/drain contact resistance202010,707,347Transistor with a negative capacitance and a method of creating the same202010,700,066Semiconductor device and manufacturing method thereof202010,693,009Structure of S/D contact and method of making same202010,672,667Semiconductor device and method202010,636,891Method of manufacturing a semiconductor device and a semiconductor device202010,535,738Semiconductor structure and manufacturing method of the same202010,515,956Semiconductor devices having Fin Field Effect Transistor (FinFET) structures and manufacturing and design methods thereof201910,497,624Method of manufacturing a semiconductor device and a semiconductor device201910,490,631Semiconductor device and fabricating method thereof201910,483,157Semiconductor device and method of manufacturing the same201910,475,902Spacers for nanowire-based integrated circuit device and method of fabricating same201910,367,094Source/drain structure having multi-facet surfaces201910,361,278Method of manufacturing a semiconductor device and a semiconductor device201910,354,998Structures and methods for fabricating semiconductor devices using fin structures201910,326,023Semiconductor device including fin structure with two channel layers and manufacturing method thereof201910,297,508Semiconductor device and method201910,290,548Semiconductor device structure with semiconductor wire201910,204,985Structure and formation method of semiconductor device structure201910,199,502Structure of S/D contact and method of making same201910,164,064FinFETs with low source/drain contact resistance201810,164,032Self-aligned contact and manufacturing method thereof201810,164,116FETs and methods for forming the same201810,163,627Semiconductor device and method for fabricating the same201810,158,020Method of forming a semiconductor device with multiple etch stop layers and inter-layer dielectrics201810,134,638FETS and methods of forming FETS201810,037,912Semiconductor device and method of manufacturing the same201810,037,994Semiconductor devices having Fin field effect transistor (FinFET) structures and manufacturing and design methods thereof201810,032,627Method for forming stacked nanowire transistors201810,008,497Method of manufacturing a semiconductor device and a semiconductor device20189,997,397Semiconductor structure and manufacturing method thereof20189,978,630Curved wafer processing method and apparatus20189,966,469Semiconductor device including fin structure with two channel layers and manufacturing method thereof20189,953,878Method of forming a semiconductor device20189,911,830'FinFETs with contact-all-around'20189,876,112Source/drain structure and manufacturing the same20189,871,037'Structures and methods for fabricating semiconductor devices using fin structures'20189,859,431'Method of forming a semiconductor device with multiple etch stop layers and inter-layer dielectrics'20189,818,878'FETs and methods for forming the same'20179,818,745'Semiconductor devices having fin field effect transistor (FinFET) structures and manufacturing and design methods thereof'20179,812,366'Method of tuning work function for a semiconductor device'20179,780,216'Combination FinFET and methods of forming same'20179,653,461'FinFETs with low source/drain contact resistance'20179,601,626'Semiconductor device including fin structure with two channel layers and manufacturing method thereof'20179,583,598'FETs and methods of forming FETs'20179,543,210'Forming crown active regions for FinFETs'20179,536,772'Fin structure of semiconductor device'20179,496,398'Epitaxial source/drain regions in FinFETs and methods for forming the same'20169,455,325'Fin field-effect transistors having controlled fin height'20169,412,814'Structure and formation method of FinFET device'20169,406,804'FinFETs with contact-all-around'20169,391,201'Source/drain structure and manufacturing the same'20169,373,704'Multiple-gate semiconductor device and method'20169,362,386'FETs and methods for forming the same'20169,293,585'Semiconductor device structure and method of forming same'20169,257,558'FinFET device with gate oxide layer'20169,257,323'Semiconductor device and method for forming the same'20169,218,650'Image processing method applicable to images captured by wide-angle zoomable lens'20159,210,400'Method and image processing device for adjusting stereo image'20159,130,058'Forming crown active regions for FinFETs'20159,105,744'Semiconductor devices having inactive fin field effect transistor (FinFET) structures and manufacturing and design methods thereof'20159,093,531'Fin structure of semiconductor device'20159,087,903'Buffer layer omega gate'20159,054,188'Curved wafer processing on method and apparatus'20159,041,158'Method of forming fin field-effect transistors having controlled fin height'20158,963,251'Semiconductor device with strain technique'20158,895,383'Multiple-gate semiconductor device and method'20148,796,666'MOS devices with strain buffer layer and methods of forming the same'20148,754,486'IO ESD device and methods for forming the same'20148,551,841'IO ESD device and methods for forming the same'20138,426,923'Multiple-gate semiconductor device and method'20138,048,764'Dual etch method of defining active area in semiconductor device'20115,513,454'Sound producing control circuit assembly for picture frames'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996Based in Chu-Nan, Miao-Li Hsien, TW· patent location history
2011–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (19)· patent assignee history
2011–2020Based in Hsinchu, TW· patent location history
2013–2015Patents assigned to LEE TUNG YING (6)· patent assignee history
2013–2015Patents assigned to GUO WEN-HUEI (4)· patent assignee history
2013–2015Patents assigned to CHANG CHIH-HAO (3)· patent assignee history
2015Based in Kaohsiung, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (71)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 71 | 2016–2020 |
| TAIWAN SEMICONDUCTOR MFG | 19 | 2011–2016 |
| LEE TUNG YINGself | 6 | 2013–2015 |
| GUO WEN-HUEI | 4 | 2013–2015 |
| CHANG CHIH-HAO | 3 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 91 | 2011–2020 |
| Kaohsiung, TW | 1 | 2015 |
| Chu-Nan, Miao-Li Hsien, TW | 1 | 1996 |