Inventor
William I. Lehrer
Inventor
Los Altos, CA, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1029%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1026%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests18%
C03CChemical composition of glasses, glazes or vitreous enamels5%
C23CCoating metallic material5%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices5%
H05KPrinted circuits5%
H10DInorganic electric semiconductor devices3%
Y10TTechnical subjects covered by former us classification3%
PatentTitleYear
4,972,251'Multilayer glass passivation structure and method for forming the same'19904,935,095'Germanosilicate spin-on glasses'19904,727,048'Process for making isolated semiconductor structure'19884,704,342'Photomask having a patterned carbon light-blocking coating'19874,654,269'Stress relieved intermediate insulating layer for multilayer metalization'19874,630,343'Product for making isolated semiconductor structure'19864,619,844'Method and apparatus for low pressure chemical vapor deposition'19864,619,839'Method of forming a dielectric layer on a semiconductor device'19864,490,737'Smooth glass insulating film over interconnects on an integrated circuit'19844,488,166'Multilayer metal silicide interconnections for integrated circuits'19844,442,449'Binary germanium-silicon interconnect and electrode structure for integrated circuits'19844,431,900'Laser induced flow Ge-O based materials'19844,420,365'Formation of patterned film over semiconductor structure'19834,417,914'Method for forming a low temperature binary glass'19834,398,335'Multilayer metal silicide interconnections for integrated circuits'19834,387,145'Lift-off shadow mask'19834,359,490'Method for LPCVD co-deposition of metal and silicon to form metal silicide'19824,267,012'Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer'1981Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1981–1990Patents assigned to FAIRCHILD CAMERA INSTR CO (16)· patent assignee history
1981–1990Based in Los Altos, CA, US· patent location history
1987Patents assigned to FAIRCHILD SEMICONDUCTOR (1)· patent assignee history
1990Patents assigned to NAT SEMICONDUCTOR CORP (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FAIRCHILD CAMERA INSTR CO | 16 | 1981–1990 |
| FAIRCHILD SEMICONDUCTOR | 1 | 1987 |
| NAT SEMICONDUCTOR CORP | 1 | 1990 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Altos, California, US | 18 | 1981–1990 |