Inventor
Shuen-Chin Chang
Inventor
San Jose, CA, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores33%
G09GArrangements or circuits for control of indicating devices using static means to present variable information23%
G06FElectric digital data processing20%
H03KPulse technique10%
H04LTransmission of digital information, e.g. telegraphic communication7%
G05FSystems for regulating electric or magnetic variables3%
H03MCoding3%
PatentTitleYear
7,167,527'System and method for multi-symbol interfacing'20077,043,657'Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle'20066,937,664'System and method for multi-symbol interfacing'20056,647,506'Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle'20036,477,592'System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream'20026,324,602'Advanced input/output interface for an integrated circuit device using two-level to multi-level signal conversion'20015,805,133'Method and apparatus for increasing the rate of scrolling in a frame buffer system designed for windowing operations'19985,654,742'Method and apparatus for providing operations affecting a frame buffer without a row address strobe cycle'19975,539,430'Pipelined read write operations in a high speed frame buffer system'19965,533,187'Multiple block mode operations in a frame buffer system designed for windowing operations'19965,528,751'Frame buffer system designed for windowing operations'19965,504,855'Method and apparatus for providing fast multi-color storage in a frame buffer'19965,500,818'Method and apparatus for providing accurate T(on) and T(off) times for the output of a memory array'19965,442,748'Architecture of output switching circuitry for frame buffer'19955,187,386'Low standby current intermediate DC voltage generator'19935,039,875'CMOS power-on reset circuit'19914,963,771'TTL/CMOS level translator'19904,630,240'Dynamic memory with intermediate column derode'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986Based in Sugarland, TX, US· patent location history
1990–1991Patents assigned to SAMSUNG SEMICONDUCTOR (2)· patent assignee history
1990–2007Based in San Jose, CA, US· patent location history
1993–1998Patents assigned to SAMSUNG SEMICONDUCTOR INC (8)· patent assignee history
1995–1998Patents assigned to SUN MICROSYSTEMS INC (8)· patent assignee history
1996Patents assigned to SAMSUNG SEMICONDUCTORS (1)· patent assignee history
2001–2007Patents assigned to INTEGRATED MEMORY LOGIC INC (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG SEMICONDUCTOR INC | 8 | 1993–1998 |
| SUN MICROSYSTEMS INC | 8 | 1995–1998 |
| INTEGRATED MEMORY LOGIC INC | 6 | 2001–2007 |
| SAMSUNG SEMICONDUCTOR | 2 | 1990–1991 |
| SAMSUNG SEMICONDUCTORS | 1 | 1996 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 17 | 1990–2007 |
| Sugarland, Texas, US | 1 | 1986 |