Inventor
Palkesh Jain
Inventor
Bangalore, IN
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing42%
H03KPulse technique19%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses8%
G01RMeasuring electric variables6%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%
G11CStatic stores3%
H01LSemiconductor devices3%
H02JElectric power networks3%
H03MCoding3%
H05KPrinted circuits3%
PatentTitleYear
10,591,965System and method for context-aware thermal management and workload scheduling in a portable computing device202010,389,379Error correcting code testing201910,141,297Integrated device comprising device level cells with variable sizes for heat dissipation around hotspots201810,103,714Adjust voltage for thermal mitigation201810,089,194System and method for false pass detection in lockstep dual core or triple modular redundancy (TMR) systems201810,042,405Adjusting source voltage based on stored information20189,915,968'Systems and methods for adaptive clock design'20189,897,651'Ultra-fast autonomous clock monitoring circuit for safe and secure automotive applications'20189,665,680'Cell-level signal electromigration'20179,628,089'Supply voltage tracking clock generator in adaptive clock distribution systems'20178,786,307'Bias temperature instability-resistant circuits'20148,677,303'Electromigration compensation system'20148,296,701'Method for designing a semiconductor device based on leakage current estimation'20128,255,850'Fabricating IC with NBTI path delay within timing constraints'20128,219,953'Budgeting electromigration-related reliability among metal paths in the design of a circuit'20128,013,635'Multi-mode circuit and a method for preventing degradation in the multi-mode circuit'20117,791,926'SEU hardening circuit and method'20107,752,582'Method and apparatus for determining electro-migration in integrated circuit designs'20107,689,377'Technique for aging induced performance drift compensation in an integrated circuit'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2014Patents assigned to TEXAS INSTRUMENTS INC (9)· patent assignee history
2010–2020Based in Bangalore, IN· patent location history
2010Based in Karnataka, IN· patent location history
2012–2017Patents assigned to JAIN PALKESH (6)· patent assignee history
2012Patents assigned to MANDAL AJOY (2)· patent assignee history
2012–2014Patents assigned to PARK YOUNG-JOON (2)· patent assignee history
2017–2020Patents assigned to QUALCOMM INC (9)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QUALCOMM INC | 9 | 2017–2020 |
| TEXAS INSTRUMENTS INC | 9 | 2010–2014 |
| JAIN PALKESHself | 6 | 2012–2017 |
| MANDAL AJOY | 2 | 2012 |
| PARK YOUNG-JOON | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bangalore, IN | 17 | 2010–2020 |
| Karnataka, IN | 2 | 2010 |