Inventor

Chew Hoe Ang

Inventor

Singapore, SG

Overview

29→

Patents

2002–2010

Patent span

Electricity

Primary field (CPC H)

Patents· 29 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices52%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%

G01RMeasuring electric variables5%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%

C30BSingle-crystal growth2%

H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%

H10BElectronic memory devices2%

PatentTitleYear

7,795,046'Method and apparatus for monitoring endcap pullback'2010 7,562,318'Test structure for automatic dynamic negative-bias temperature instability testing'2009 7,479,425'Method for forming high-K charge storage device'2009 7,326,609'Semiconductor device and fabrication method'2008 7,202,140'Method to fabricate Ge and Si devices together for performance enhancement'2007 7,176,094'Ultra-thin gate oxide through post decoupled plasma nitridation anneal'2007 7,132,878'Charge pump current source'2006 7,103,861'Test structure for automatic dynamic negative-bias temperature instability testing'2006 7,095,073'High K artificial lattices for capacitor applications to use in Cu or Al BEOL'2006 7,022,625'Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration'2006 6,841,441'Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing'2005 6,830,971'High K artificial lattices for capacitor applications to use in CU or AL BEOL'2004 6,828,082'Method to pattern small features by using a re-flowable hard mask'2004 6,762,085'Method of forming a high performance and low cost CMOS device'2004 6,743,291'Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth'2004 6,734,082'Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape'2004 6,709,912'Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization'2004 6,670,248'Triple gate oxide process with high-k gate dielectric'2003 6,664,153'Method to fabricate a single gate with dual work-functions'2003 6,664,156'Method for forming L-shaped spacers with precise width control'2003 6,632,712'Method of fabricating variable length vertical transistors'2003 6,610,575'Forming dual gate oxide thickness on vertical transistors by ion implantation'2003 6,610,604'Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask'2003 6,605,501'Method of fabricating CMOS device with dual gate electrode'2003 6,586,314'Method of forming shallow trench isolation regions with improved corner rounding'2003 6,544,848'Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers'2003 6,468,851'Method of fabricating CMOS device with dual gate electrode'2002 6,429,109'Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate'2002 6,403,425'Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxide'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2009Patents assigned to CHARTERED SEMICONDUCTOR MFG (28)· patent assignee history

2002–2010Based in Singapore, SG· patent location history

2010Patents assigned to ADVANCED MICRO DEVICES INC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
CHARTERED SEMICONDUCTOR MFG	28	2002–2009
ADVANCED MICRO DEVICES INC	1	2010

Locations

Location	Patents	Span
Singapore, SG	29	2002–2010