Inventor
Kevin D. Lucas
Inventor
Austin, TX, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G03Fprimary
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices50%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
G06FElectric digital data processing11%
H10DInorganic electric semiconductor devices11%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
PatentTitleYear
8,370,773'Method and apparatus for designing an integrated circuit using inverse lithography technology'20138,312,394'Method and apparatus for determining mask layouts for a spacer-is-dielectric self-aligned double-patterning process'20128,175,737'Method and apparatus for designing and integrated circuit'20127,962,868'Method for forming a semiconductor device using optical proximity correction for the optical lithography'20117,935,547'Method of patterning a layer using a pellicle'20117,284,231'Layout modification using multilayer-based constraints'20076,989,229'Non-resolving mask tiling method for flare reduction'20066,933,227'Semiconductor device and method of forming the same'20056,818,362'Photolithography reticle design'20046,783,904'Lithography correction method and device'20046,649,452'Method for manufacturing a lithographic reticle for transferring an integrated circuit design to a semiconductor wafer'20036,294,820'Metallic oxide gate electrode stack having a metallic gate dielectric metallic gate electrode and a metallic arc layer'20016,287,951'Process for forming a combination hardmask and antireflective layer'20016,174,810'Copper interconnect structure and method of formation'20016,004,850'Tantalum oxide anti-reflective coating (ARC) integrated with a metallic transistor gate electrode and method of formation'19995,958,635'Lithographic proximity correction through subset feature modification'19995,920,487'Two dimensional lithographic proximity correction using DRC shape functions'19995,900,340'One dimensional lithographic proximity correction using DRC shape functions'19995,849,440'Process for producing and inspecting a lithographic reticle and fabricating semiconductor devices using same'19985,827,625'Methods of designing a reticle and forming a semiconductor device therewith'19985,741,626'Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC)'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2003Patents assigned to MOTOROLA INC (11)· patent assignee history
1998–2012Based in Austin, TX, US· patent location history
2004–2013Patents assigned to FREESCALE SEMICONDUCTOR INC (9)· patent assignee history
2004–2013Based in Meylan, FR· patent location history
2012–2013Patents assigned to BOONE ROBERT ELLIOTT (2)· patent assignee history
2012–2013Patents assigned to KONINKL PHILIPS ELECTRONICS NV (2)· patent assignee history
2012–2013Patents assigned to LUCAS KEVIN DEAN (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MOTOROLA INC | 11 | 1998–2003 |
| FREESCALE SEMICONDUCTOR INC | 9 | 2004–2013 |
| BOONE ROBERT ELLIOTT | 2 | 2012–2013 |
| KONINKL PHILIPS ELECTRONICS NV | 2 | 2012–2013 |
| LUCAS KEVIN DEANself | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 15 | 1998–2012 |
| Meylan, FR | 6 | 2004–2013 |