Inventor
Dean D. Gans
Inventor
Nampa, ID, US
Overview
Patents· 96 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores44%
G06FElectric digital data processing23%
H03KPulse technique15%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%
H04LTransmission of digital information, e.g. telegraphic communication4%
G01RMeasuring electric variables1%
H03HImpedance networks, e.g. resonant circuits1%
H10DInorganic electric semiconductor devices1%
H04BTransmission1%
PatentTitleYear
11,121,714Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance202111,087,819Methods for row hammer mitigation and memory devices and systems employing the same202111,088,895Methods and apparatuses for signal translation in a buffered memory202111,037,617Methods for row hammer mitigation and memory devices and systems employing the same202111,017,879Adjustable column address scramble using fuses202111,010,092Prefetch signaling in memory system or sub-system202111,003,388Prefetch signaling in memory system or sub system202110,976,945Memory devices with multiple sets of latencies and methods for operating the same202110,978,115Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters202110,978,116Multiple concurrent modulation schemes in a memory system202110,963,168Memory system and operations of the same202110,956,333Prefetching data based on data transfer within a memory system202110,942,854Prefetch management for memory202110,915,474Apparatuses and methods including memory commands for semiconductor memories202110,910,037Apparatuses and methods for input receiver circuits and receiver masks for same202110,904,052Multiplexing distinct signals on a single pin of a memory device202110,868,519Apparatuses and methods for calibrating adjustable impedances of a semiconductor device202010,839,874Indicating latency associated with a memory request in a system202010,832,748Memory system that supports dual-mode modulation202010,825,485Apparatuses and methods for power efficient driver circuits202010,796,746Frequency synthesis for memory input-output operations202010,788,985Apparatuses and methods for configurable memory array bank architectures202010,789,186Apparatuses and methods including memory commands for semiconductor memories202010,754,578Memory buffer management and bypass202010,725,913Variable modulation scheme for memory device access or operation202010,714,159Indication in memory system or sub-system of latency associated with performing an access command202010,715,127Apparatuses and methods for using look-ahead duty cycle correction to determine duty cycle adjustment values while a semiconductor device remains in operation202010,700,918Methods and apparatuses for signal translation in a buffered memory202010,649,687Memory buffer management and bypass202010,629,245Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters202010,615,798Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance202010,541,019Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory202010,490,245Memory system that supports dual-mode modulation201910,481,819Memory devices with multiple sets of latencies and methods for operating the same201910,467,158Apparatuses and methods including memory commands for semiconductor memories201910,446,198Multiple concurrent modulation schemes in a memory system201910,424,351Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters201910,394,473Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination201910,387,341Apparatuses and methods for asymmetric input/output interface for a memory201910,381,050Apparatuses and methods for power efficient driver circuits201910,372,330Apparatuses and methods for configurable memory array bank architectures201910,355,893Multiplexing distinct signals on a single pin of a memory device201910,348,270Apparatuses and methods for calibrating adjustable impedances of a semiconductor device201910,256,817Methods and systems for averaging impedance calibration201910,180,920Apparatuses and methods for asymmetric input/output interface for a memory201910,164,817Methods and apparatuses for signal translation in a buffered memory201810,157,647Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters201810,115,449Frequency synthesis for memory input-output operations201810,090,836Methods and systems for averaging impedance calibration20189,978,437Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory20189,965,408Apparatuses and methods for asymmetric input/output interface for a memory20189,935,632Methods and systems for averaging impedance calibration20189,934,831Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters20189,911,469'Apparatuses and methods for power efficient driver circuits'20189,766,831'Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination'20179,601,182'Frequency synthesis for memory input-output operations'20179,508,409'Apparatuses and methods for implementing masked write commands'20168,599,629'Method and apparatus for synchronizing data from memory arrays'20138,248,870'Method and apparatus for synchronizing data from memory arrays'20127,660,172'Method and apparatus for synchronizing data from memory arrays'20107,489,165'Method and apparatus for amplifying a regulated differential signal to a higher voltage'20097,362,627'Method and apparatus for synchronizing data from memory arrays'20087,285,986'High speed, low power CMOS logic gate'20077,274,220'Method and apparatus for amplifying a regulated differential signal to a higher voltage'20077,215,585'Method and apparatus for synchronizing data from memory arrays'20077,050,342'Testmode to increase acceleration in burn-in'20067,046,038'Upward and downward pulse stretcher circuits and modules'20066,982,572'Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges, circuits and systems including same'20066,972,589'Method for rapidly propagating a fast edge of an output signal through a skewed logic device'20056,965,255'Method and apparatus for amplifying a regulated differential signal to a higher voltage'20056,949,948'Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges'20056,937,066'Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges'20056,919,735'Skewed nor and nand rising logic devices for rapidly propagating a rising edge of an output signal'20056,917,222'Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges and systems including same'20056,891,398'Skewed falling logic device for rapidly propagating a falling edge of an output signal'20056,812,746'Method and apparatus for amplifying a regulated differential signal to a higher voltage'20046,724,218'Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges'20046,725,316'Method and apparatus for combining architectures with logic option'20046,628,139'Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges'20036,621,755'Testmode to increase acceleration in burn-in'20036,507,924'Method and apparatus for testing SRAM memory cells'20036,438,043'Adjustable I/O timing from externally applied voltage'20026,388,926'Integrated circuit having forced substrate test mode with improved substrate isolation'20026,353,521'Device and method for protecting an integrated circuit during an ESD event'20026,317,381'Method and system for adaptively adjusting control signal timing in a memory device'20016,304,511'Method and apparatus for adjusting control signal timing in a memory device'20016,272,064'Memory with combined synchronous burst and bus efficient functionality'20016,163,500'Memory with combined synchronous burst and bus efficient functionality'20006,161,204'Method and apparatus for testing SRAM memory cells'20006,130,811'Device and method for protecting an integrated circuit during an ESD event'20006,111,812'Method and apparatus for adjusting control signal timing in a memory device'20005,999,466'Method, apparatus and system for voltage screening of integrated circuits'19995,978,311'Memory with combined synchronous burst and bus efficient functionality'19995,933,378'Integrated circuit having forced substrate test mode with improved substrate isolation'19995,905,682'Method and apparatus for biasing the substrate of an integrated circuit to an externally adjustable voltage'19995,757,713'Adjustable write voltage circuit for SRAMS'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2021Patents assigned to MICRON TECHNOLOGY INC (96)· patent assignee history
1998–2009Based in Boise, ID, US· patent location history
2007–2021Based in Nampa, ID, US· patent location history
2012–2013Patents assigned to GANS DEAN (2)· patent assignee history
2012–2013Patents assigned to LOVETT SIMON J (2)· patent assignee history
2019Based in Nampe, ID, US· patent location history
2020Patents assigned to MICRO TECH INC (1)· patent assignee history
2021Patents assigned to MICROON TECH INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 96 | 1998–2021 |
| GANS DEANself | 2 | 2012–2013 |
| LOVETT SIMON J | 2 | 2012–2013 |
| MICRO TECH INC | 1 | 2020 |
| MICROON TECH INC | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Nampa, ID, US | 62 | 2007–2021 |
| Boise, ID, US | 33 | 1998–2009 |
| Nampe, ID, US | 1 | 2019 |