Inventor
Jerome B. Lasky
Inventor
Essex Junction, VT, US
Overview
Patents· 31 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices32%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation11%
H10BElectronic memory devices9%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems4%
G11CStatic stores2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
PatentTitleYear
7,696,586'Cobal disilicide structure'20107,652,313'Deep trench contact and isolation of buried photodetectors'20107,572,701'Recessed gate for a CMOS image sensor'20097,492,048'CMOS sensors having charge pushing regions'20097,459,360'Method of forming pixel sensor cell having reduced pinning layer barrier potential'20087,411,258'Cobalt disilicide structure'20087,217,968'Recessed gate for an image sensor'20077,205,591'Pixel sensor cell having reduced pinning layer barrier potential and method thereof'20077,183,573'Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet'20077,173,303'FIN field effect transistor with self-aligned gate'20076,727,118'Power distribution design method for stacked flip-chip packages'20046,689,650'Fin field effect transistor with self-aligned gate'20046,660,596'Double planar gated SOI MOSFET structure'20036,635,970'Power distribution design method for stacked flip-chip packages'20036,483,156'Double planar gated SOI MOSFET structure'20026,436,744'Method and structure for creating high density buried contact for use with SOI processes for high performance logic'20026,339,005'Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET'20026,335,294'Wet cleans for cobalt disilicide processing'20026,335,272'Buried butted contact and method for fabricating'20026,328,794'Method of controlling stress in a film'20016,197,656'Method of forming planar isolation and substrate contacts in SIMOX-SOI.'20016,153,934'Buried butted contact and method for fabricating'20006,140,171'FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication'20006,038,168'Hot-electron programmable latch for integrated circuit fuse applications and method of programming therefor'20006,022,766'Semiconductor structure incorporating thin film transistors, and methods for its manufacture'20006,015,745'Method for semiconductor fabrication'20005,913,125'Method of controlling stress in a film'19995,894,169'Low-leakage borderless contacts to doped regions'19995,605,862'Process for making low-leakage contacts'19975,545,581'Plug strap process utilizing selective nitride and oxide etches'19965,185,294'Boron out-diffused surface strap process'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–2010Patents assigned to IBM (31)· patent assignee history
1993–2010Based in Essex Junction, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 31 | 1993–2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 31 | 1993–2010 |