Inventor
Raguram Damodaran
Inventor
Plano, TX, US
Overview
Patents· 59 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing32%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use20%
H03KPulse technique15%
H03MCoding14%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications9%
G11CStatic stores7%
G01RMeasuring electric variables3%
PatentTitleYear
10,713,180Lookahead priority collection to support priority elevation202010,635,446Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction202010,551,896Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase202010,474,462Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructions201910,223,118Providing references to previously decoded instructions of recently-provided instructions to be executed by a processor201910,203,745Apparatus and method for dynamic power reduction in a unified scheduler201910,108,417Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor201810,089,114Multiple instruction issuance with parallel inter-group and intra-group picking20189,965,395Memory attribute sharing between differing cache levels of multilevel cache20189,851,774Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase20179,830,152Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processor20179,582,285'Speculative history forwarding in overriding branch predictors, and related circuits, methods, and computer-readable media'20179,575,901'Programmable address-based write-through cache control'2017RE046193'Distributed power control for controlling power consumption based on detected activity of logic blocks'20169,390,011'Zero cycle clock invalidate operation'20169,298,643'Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty'20169,268,708'Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence'20169,244,837'Zero cycle clock invalidate operation'20169,195,610'Transaction info bypass for nodes coupled to an interconnect fabric'20159,189,331'Programmable address-based write-through cache control'20159,183,084'Memory attribute sharing between differing cache levels of multilevel cache'20159,075,743'Managing bandwidth allocation in a processing node using distributed arbitration'20159,075,744'Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty'20159,021,320'pBIST architecture with multiple asynchronous sub chips operating in differing voltage domains'20159,009,550'pBIST engine with distributed data logging'20159,009,408'Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache system'20159,003,122'Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence'20158,977,821'Parallel processing of multiple block coherence operations'20158,977,915'pBIST engine with reduced SRAM testing bus width'20158,970,267'Asynchronous clock dividers to reduce on-chip variations of clock timing'20158,930,783'pBIST read only memory image compression'20158,904,115'Cache with multiple access pipelines'20148,904,110'Distributed user controlled multilevel block and global cache coherence with accurate completion status'20148,904,249'At speed testing of high performance memories with a multi-port BIS engine'20148,862,835'Multi-port register file with an input pipelined architecture and asynchronous read data forwarding'20148,862,836'Multi-port register file with an input pipelined architecture with asynchronous reads and localized feedback'20148,856,446'Hazard prevention for data conflicts between level one data cache line allocates and snoop writes'20148,732,416'Requester based transaction status reporting in a system with multi-level memory'20148,732,398'Enhanced pipelining and multi-buffer architecture for level two cache controller to minimize hazard stalls and optimize performance'20148,707,127'Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines'20148,656,105'Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers'20148,598,932'Integer and half clock step division digital variable clock divider'20138,582,384'Process variability tolerant programmable memory controller for a pipelined memory system'20138,560,896'Priority based exception mechanism for multi-level cache controller'20138,532,247'Integer and half clock step division digital variable clock divider'20138,488,405'Process variability tolerant programmable memory controller for a pipelined memory system'20138,201,004'Entry/exit control to/from a low power state in a complex multi level memory system'20127,805,644'Multiple pBIST controllers'20107,603,487'Hardware configurable hub interface unit'20097,487,421'Emulation cache access for tag view reads'20097,475,313'Unique pBIST features for advanced memory testing'20097,444,573'VLCT programmation/read protocol'20087,325,178'Programmable built in self test of memory'20087,324,392'ROM-based memory testing'20087,277,808'Process parameter based I/O timing programmability using electrical fuse elements'20077,240,277'Memory error detection reporting'20077,158,902'Process parameter based I/O timing programmability using electrical fuse elements'20076,985,982'Active ports in a transfer controller with hub and ports'20066,594,713'Hub interface unit and application unit interfaces for expanded direct memory access processor'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2020Patents assigned to TEXAS INSTRUMENTS INC (49)· patent assignee history
2003–2020Based in Plano, TX, US· patent location history
2012–2015Patents assigned to DAMODARAN RAGURAM (22)· patent assignee history
2013–2015Patents assigned to CHACHAD ABHIJEET ASHOK (14)· patent assignee history
2013–2018Based in Raleigh, NC, US· patent location history
2014–2015Patents assigned to BHORIA NAVEEN (6)· patent assignee history
2017–2020Patents assigned to QUALCOMM INC (10)· patent assignee history
2017–2020Based in San Diego, CA, US· patent location history
2020Based in La Jolla, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 49 | 2003–2020 |
| DAMODARAN RAGURAMself | 22 | 2012–2015 |
| CHACHAD ABHIJEET ASHOK | 14 | 2013–2015 |
| QUALCOMM INC | 10 | 2017–2020 |
| BHORIA NAVEEN | 6 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Plano, Texas, US | 42 | 2003–2020 |
| San Diego, California, US | 8 | 2017–2020 |
| Raleigh, NC, US | 8 | 2013–2018 |
| La Jolla, California, US | 1 | 2020 |