Inventor
Steev Wilcox
Inventor
San Jose, CA, US
Overview
Patents· 9 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G01Rprimary
G01RMeasuring electric variables75%
G06FElectric digital data processing25%
PatentTitleYear
9,817,069'Method and system for construction of a highly efficient and predictable sequential test decompression logic'20179,817,068'Method and system for improving efficiency of sequential test compression using overscan'20179,606,179'Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer'20179,513,335'Method for using XOR trees for physically efficient scan compression and decompression logic'20169,501,590'Systems and methods for testing integrated circuit designs'20169,470,756'Method for using sequential decompression logic for VLSI test in a physically efficient construction'20169,470,755'Method for dividing testable logic into a two-dimensional grid for physically efficient scan'20169,470,754'Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization'20169,465,896'Systems and methods for testing integrated circuit designs'2016Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2016–2017Patents assigned to CADENCE DESIGN SYSTEMS INC (9)· patent assignee history
2016–2017Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CADENCE DESIGN SYSTEMS INC | 9 | 2016–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 9 | 2016–2017 |