Inventor
Jeong Yeol Choi
Inventor
Palo Alto, CA, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices36%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10BElectronic memory devices9%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
C23CCoating metallic material2%
C30BSingle-crystal growth2%
G06FElectric digital data processing2%
G11CStatic stores2%
PatentTitleYear
7,378,289'Method for forming photomask having test patterns in blading areas'20087,316,537'Substrate transport apparatus'20087,125,775'Method for forming hybrid device gates'20066,898,561'Methods, apparatus and computer program products for modeling integrated circuit devices having reduced linewidths'20056,894,356'SRAM system having very lightly doped SRAM load transistors for improving SRAM cell stability and method for making the same'20056,496,399'Compact ternary content addressable memory cell'20026,407,008'Method of forming an oxide layer'20026,258,693'Ion implantation for scalability of isolation in an integrated circuit'20016,191,460'Identical gate conductivity type static random access memory cell'20016,165,918'Method for forming gate oxides of different thicknesses'20006,127,710'CMOS structure having a gate without spacers'20006,103,555'Method of improving the reliability of low-voltage programmable antifuse'20006,069,054'Method for forming isolation regions subsequent to gate formation and structure thereof'20006,063,676'Mosfet with raised source and drain regions'20006,043,129'High density MOSFET with raised source and drain regions'20006,017,785'Method for improving latch-up immunity and interwell isolation in a semiconductor device'20005,926,704'Efficient method for fabricating P-wells and N-wells'19995,888,861'Method of manufacturing a BiCMOS integrated circuit fully integrated within a CMOS process flow'19995,830,789'CMOS process forming wells after gate formation'19985,831,313'Structure for improving latch-up immunity and interwell isolation in a semiconductor device'19985,793,088'Structure for controlling threshold voltage of MOSFET'19985,780,330'Selective diffusion process for forming both n-type and p-type gates with a single masking step'19985,750,424'Method for fabricating a CMOS device'19985,679,588'Method for fabricating P-wells and N-wells having optimized field and active regions'19975,654,213'Method for fabricating a CMOS device'19975,393,677'Method of optimizing wells for PMOS and bipolar to yield an improved BICMOS process'19955,128,731'Static random access memory cell using a P/N-MOS transistors'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2008Patents assigned to INTEGRATED DEVICE TECH (26)· patent assignee history
1992–2000Based in Fremont, CA, US· patent location history
1998–2008Based in Palo Alto, CA, US· patent location history
2005Based in Portland, OR, US· patent location history
2008Patents assigned to SEMES CO LTD (1)· patent assignee history
2008Based in Cheonan-si, KR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEGRATED DEVICE TECH | 26 | 1992–2008 |
| SEMES CO LTD | 1 | 2008 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 13 | 1998–2008 |
| Fremont, California, US | 12 | 1992–2000 |
| Cheonan-si, KR | 1 | 2008 |
| Portland, OR, US | 1 | 2005 |