Inventor

Jonathan Greene

Inventor

Palo Alto, CA, US

Overview

54→

Patents

1989–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 54 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary

H03KPulse technique38%

G11CStatic stores15%

H10BElectronic memory devices9%

H10NElectric solid-state devices not otherwise provided for9%

G06FElectric digital data processing8%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%

H01LSemiconductor devices5%

G01RMeasuring electric variables4%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%

B29CShaping or joining of plastics1%

PatentTitleYear

10,967,589Tire mold with interchangeable element having removably attachable lamelle2021 10,855,286Front to back resistive random-access memory cells2020 10,714,180Hybrid configuration memory cell2020 10,523,208Efficient lookup table modules for user-programmable integrated circuits2019 10,361,702FPGA math block with dedicated connections2019 10,256,822Front to back resistive random access memory cells2019 10,020,811FPGA RAM blocks optimized for use as register files2018 9,991,894Resistive random access memory cells2018 9,780,792'FPGA RAM blocks optimized for use as register files'2017 9,514,804'Multi-state configuration RAM cell'2016 9,170,774'Fast carry lookahead circuits'2015 9,147,025'Method for efficient FPGA packing'2015 9,147,836'Layouts for resistive RAM cells'2015 9,103,880'On-chip probe circuit for detecting faults in an FPGA'2015 9,000,807'On-chip probe circuit for detecting faults in an FPGA'2015 8,981,328'Back to back resistive random access memory cells'2015 8,868,820'RAM block designed for efficient ganging'2014 8,723,151'Front to back resistive random access memory cells'2014 8,446,170'FPGA RAM blocks optimized for use as register files'2013 8,415,650'Front to back resistive random access memory cells'2013 8,269,203'Resistive RAM devices for programmable logic devices'2012 8,269,204'Back to back resistive random access memory cells'2012 8,244,791'Fast carry lookahead circuits'2012 8,085,064'Logic module including versatile adder for FPGA'2011 7,932,745'Inverting flip-flop for use in field programmable gate arrays'2011 7,932,744'Staggered I/O groups for integrated circuits'2011 7,924,052'Field programmable gate array architecture having Clos network-based input interconnect'2011 7,919,977'Circuits and methods for testing FPGA routing switches'2011 7,884,640'PLD providing soft wakeup logic'2011 7,816,946'Inverting flip-flop for use in field programmable gate arrays'2010 7,804,321'Circuits and methods for testing FPGA routing switches'2010 7,772,879'Logic module including versatile adder for FPGA'2010 7,581,117'Method for secure delivery of configuration data for a programmable logic device'2009 7,573,746'Volatile data storage in a non-volatile memory cell array'2009 7,538,576'Non-volatile look-up table for an FPGA'2009 7,495,473'Non-volatile look-up table for an FPGA'2009 7,492,182'Non-volatile look-up table for an FPGA'2009 7,463,061'Apparatus and method for reducing leakage of unused buffers in an integrated circuit'2008 7,443,198'Non-volatile look-up table for an FPGA'2008 7,430,137'Non-volatile memory cells in a field programmable gate array'2008 7,321,237'Non-volatile look-up table for an FPGA'2008 7,301,821'Volatile data storage in a non-volatile memory cell array'2007 7,129,748'Non-volatile look-up table for an FPGA'2006 5,781,033'Logic module with configurable combinational and sequential blocks'1998 5,610,534'Logic module for a programmable logic device'1997 5,440,245'Logic module with configurable combinational and sequential blocks'1995 5,198,705'Logic module with configurable combinational and sequential blocks'1993 5,191,241'Programmable interconnect architecture'1993 5,132,571'Programmable interconnect architecture having interconnects disposed above function modules'1992 5,095,228'Circuits for preventing breakdown of low-voltage device inputs during high voltage antifuse programming'1992 5,055,718'Logic module with configurable combinational and sequential blocks'1991 5,017,813'Input/output module with latches'1991 4,910,417'Universal logic module comprising multiplexers'1990 4,873,459'Programmable interconnect architecture'1989

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1989–2013Patents assigned to ACTEL CORP (35)· patent assignee history

1989–2020Based in Palo Alto, CA, US· patent location history

2011–2015Patents assigned to GREENE JONATHAN (8)· patent assignee history

2012–2013Patents assigned to HAWLEY FRANK W (3)· patent assignee history

2012–2015Patents assigned to HECHT VOLKER (3)· patent assignee history

2014–2020Patents assigned to MICROSEMI SOC CORP (17)· patent assignee history

2021Based in Spartanburg, SC, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ACTEL CORP	35	1989–2013
MICROSEMI SOC CORP	17	2014–2020
GREENE JONATHANself	8	2011–2015
HAWLEY FRANK W	3	2012–2013
HECHT VOLKER	3	2012–2015

Locations

Location	Patents	Span
Palo Alto, California, US	53	1989–2020
Spartanburg, SC, US	1	2021