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Inventor

Nori Ogura

Inventor
Hillsboro, OR, US

Overview

27→
Patents
2003–2015
Patent span
Physics
Primary field (CPC G)

Patents· 27 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores68%
H10BElectronic memory devices20%
H10DInorganic electric semiconductor devices10%
H01LSemiconductor devices3%
PatentTitleYear
9,153,592'High density vertical structure nitride flash memory'20159,123,419'Complementary reference method for high reliability trap-type non-volatile memory'20158,710,576'High density vertical structure nitride flash memory'20148,633,544'Twin MONOS array for high speed application'20148,325,542'Complementary reference method for high reliability trap-type non-volatile memory'20128,174,885'High speed operation method for twin MONOS metal bit array'20128,139,410'Trap-charge non-volatile switch connector for programmable logic'20128,089,809'Trap-charge non-volatile switch connector for programmable logic'20128,027,198'Trap-charge non-volatile switch connector for programmable logic'20118,023,326'Trap-charge non-volatile switch connector for programmable logic'20117,936,604'High speed operation method for twin MONOS metal bit array'20117,742,336'Trap-charge non-volatile switch connector for programmable logic'20107,447,077'Referencing scheme for trap memory'20087,352,033'Twin MONOS array for high speed application'20087,301,820'Non-volatile memory dynamic operations'20077,190,603'Nonvolatile memory array organization and usage'20077,046,553'Fast program to program verify method'20066,856,545'Fast program to program verify method'20056,807,105'Fast program to program verify method'20046,735,118'CG-WL voltage boosting scheme for twin MONOS'20046,636,438'Control gate decoder for twin MONOS memory with two bit erase capability'20036,636,439'Fast program to program verify method'20036,631,089'Bit line decoding scheme and circuit for dual bit memory array'20036,628,547'Fast program to program verify method'20036,628,546'Fast program to program verify method'20036,611,461'Fast program to program verify method'20036,549,463'Fast program to program verify method'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2015Patents assigned to HALO LSI INC (26)· patent assignee history
2003–2006Based in Wappingers Falls, NY, US· patent location history
2003–2004Based in Hopewell Jct., NY, US· patent location history
2007–2015Based in Hillsboro, OR, US· patent location history
2012–2014Patents assigned to OGURA NORI (6)· patent assignee history
2012–2014Patents assigned to OGURA SEIKI (5)· patent assignee history
2012–2014Patents assigned to OGURA TOMOKO (5)· patent assignee history
2012–2014Patents assigned to BABA YOSHITAKA (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
HALO LSI INC262003–2015
OGURA NORIself62012–2014
OGURA SEIKI52012–2014
OGURA TOMOKO52012–2014
BABA YOSHITAKA22012–2014
Locations
LocationPatentsSpan
Hillsboro, OR, US162007–2015
Wappingers Falls, New York, US82003–2006
Hopewell Jct., New York, US32003–2004