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Inventor

William Y. Chen

Inventor
Sunnyvale, CA, US

Overview

19→
Patents
1997–2019
Patent span
Physics
Primary field (CPC G)

Patents· 19 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing95%
G11CStatic stores5%
PatentTitleYear
10,289,394Selective generation of multiple versions of machine code for source code functions for execution on different processor versions and/or architectures20199,766,911'Support for a non-native application'20179,146,831'Sampling based runtime optimizer for efficient debugging of applications'20158,627,302'Sampling based runtime optimizer for efficient debugging of applications'20148,521,760'Dynamic translator for requests for system resources'20138,473,930'Handling signals and exceptions in a dynamic translation environment'20138,346,531'Handling mutex locks in a dynamic binary translation across heterogeneous computer systems'20138,230,402'Testing and debugging of dynamic binary translation'20128,090,916'In-circuit programming architecture with processor and delegable flash controller'20128,020,155'Mechanism for optimizing function execution'20117,406,559'In-circuit programming architecture with processor, delegable flash controller, and code generator'20086,732,356'System and method of using partially resolved predicates for elimination of comparison instruction'20046,637,026'Instruction reducing predicate copy'20036,631,465'Method and apparatus for instruction re-alignment using a branch on a falsehood of a qualifying predicate'20036,631,460'Advanced load address table entry invalidation based on register address wraparound'20036,505,345'Optimization of initialization of parallel compare predicates in a computer system'20036,351,849'Compiler optimization through combining of memory operations'20025,903,749'Method and apparatus for implementing check instructions that allow for the reuse of memory conflict information if no memory conflict occurs'19995,694,577'Memory conflict buffer for achieving memory disambiguation in compile-time code schedule'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2011Based in Sunnyvale, CA, US· patent location history
2002–2004Patents assigned to INTEL CORP (5)· patent assignee history
2008–2012Based in Hsinchu, TW· patent location history
2011–2017Patents assigned to ORACLE AMERICA INC (8)· patent assignee history
2012–2017Patents assigned to CHEN WILLIAM Y (6)· patent assignee history
2012–2017Patents assigned to LU JIWEI (6)· patent assignee history
2012–2019Based in Los Altos, CA, US· patent location history
2013–2017Patents assigned to BANERJEE CHANDRAMOULI (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ORACLE AMERICA INC82011–2017
CHEN WILLIAM Yself62012–2017
LU JIWEI62012–2017
INTEL CORP52002–2004
BANERJEE CHANDRAMOULI42013–2017
Locations
LocationPatentsSpan
Sunnyvale, California, US91997–2011
Los Altos, California, US82012–2019
Hsinchu, TW22008–2012