LexDanaLexDanabeta
Inventor

Sandeep Kumar Goel

Inventor
Dublin, CA, US

Overview

72→
Patents
2006–2020
Patent span
Physics
Primary field (CPC G)

Patents· 72 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G01Rprimary
G01RMeasuring electric variables30%
G06FElectric digital data processing18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
H01LSemiconductor devices9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
G11CStatic stores5%
H03KPulse technique4%
H05KPrinted circuits2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
Y10TTechnical subjects covered by former us classification2%
PatentTitleYear
10,871,518Systems and methods for determining systematic defects202010,867,098System and method for ESL modeling of machine learning202010,867,089Electrical system level (ESL) battery discharge simulation202010,782,318Test probing structure202010,776,538Function safety and fault management modeling at electrical system level (ESL)202010,719,648System and method for system-level parameter estimation202010,685,157Power-aware scan partitioning202010,680,627Phase-locked loop monitor circuit202010,666,578Network-on-chip system and a method of generating the same202010,539,617Scan architecture for interconnect testing in 3D integrated circuits202010,440,281Image processing apparatus on integrated circuit and method thereof201910,371,751Circuit and method for diagnosing scan chain failures201910,345,883Power estimation201910,267,857Method and system for functional safety verification201910,256,828Phase-locked loop monitor circuit201910,156,609Device and method for robustness verification201810,156,607Bidirectional scan chain structure and method201810,115,643Circuit and method for monolithic stacked integrated circuit testing201810,108,764Power consumption estimation method for system on chip (SOC), system for implementing the method201810,101,796Processor power estimation201810,078,720Methods and systems for circuit fault diagnosis201810,061,374Dynamic frequency scaling20189,835,680Method, device and computer program product for circuit testing20179,830,413System and method for estimating performance, power, area and cost (PPAC)20179,817,029'Test probing structure'20179,811,627'Method of component partitions on system on chip and device thereof'20179,791,510'Circuit and method for diagnosing scan chain failures'20179,704,766'Interposers of 3-dimensional integrated circuit package systems and methods of designing the same'20179,686,852'Multi-dimensional integrated circuit structures and methods of forming the same'20179,651,621'System for and method of semiconductor fault detection'20179,647,028'Wafer on wafer stack method of forming and method of using the same'20179,646,128'System and method for validating stacked dies by comparing connections'20179,633,147'Power state coverage metric and method for estimating the same'20179,625,971'System and method of adaptive voltage frequency scaling'20179,625,523'Method and apparatus for interconnect test'20179,612,277'System and method for functional verification of multi-die 3D ICs'20179,599,670'Circuit and method for monolithic stacked integrated circuit testing'20179,513,332'Probe card partition scheme'20169,514,268'Interposer defect coverage metric and method to maximize the same'20169,404,971'Circuit and method for monolithic stacked integrated circuit testing'20169,391,110'Wafer on wafer stack method of forming and method of using the same'20169,390,219'System for and method of semiconductor fault detection'20169,341,672'Method and apparatus for interconnect test'20169,222,983'Circuit and method for monolithic stacked integrated circuit testing'20159,194,913'Circuit and method for diagnosing scan chain failures'20159,158,881'Interposer defect coverage metric and method to maximize the same'20159,110,136'Circuit and method for monolithic stacked integrated circuit testing'20159,054,101'Multi-dimensional integrated circuit structures and methods of forming the same'20159,047,432'System and method for validating stacked dies by comparing connections'20159,041,411'Testing of an integrated circuit that contains secret information'20158,972,918'System and method for functional verification of multi-die 3D ICs'20158,966,419'System and method for testing stacked dies'20158,914,692'DRAM test architecture for wide I/O DRAM based 2.5D/3D system chips'20148,873,320'DRAM repair architecture for wide I/O DRAM based 2.5D/3D system chips'20148,836,363'Probe card partition scheme'20148,826,202'Reducing design verification time while maximizing system functional coverage'20148,751,994'System and method for testing stacked dies'20148,707,238'Method to determine optimal micro-bump-probe pad pairing for efficient PGD testing in interposer designs'20148,686,570'Multi-dimensional integrated circuit structures and methods of forming the same'20148,627,160'System and device for reducing instantaneous voltage droop during a scan shift operation'20148,578,309'Format conversion from value change dump (VCD) to universal verification methodology (UVM)'20138,566,766'Method for detecting small delay defects'20138,566,657'Circuit and method for diagnosing scan chain failures'20138,561,001'System and method for testing stacked dies'20138,552,734'Test prepared integrated circuit with an internal power supply domain'20138,515,695'Method and an apparatus for evaluating small delay defect coverage of a test pattern set on an IC'20138,436,639'Circuits and methods for testing through-silicon vias'20138,402,404'Stacked die interconnect validation'20138,352,818'Method for generating test patterns for small delay defects'20138,140,923'Test circuit and method for testing of infant mortality related defects'20127,380,181'Test circuit and method for hierarchical core'20087,076,709'Testing of circuit with plural clock domains'2006

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2006–2015Based in Eindhoven, NL· patent location history
2012–2018Patents assigned to GOEL SANDEEP KUMAR (22)· patent assignee history
2012–2013Based in Milpitas, CA, US· patent location history
2013–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (19)· patent assignee history
2013–2018Patents assigned to MEHTA ASHOK (5)· patent assignee history
2013–2018Patents assigned to JOHN STANLEY (4)· patent assignee history
2013–2020Based in Dublin, CA, US· patent location history
2013–2018Based in San Jose, CA, US· patent location history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (45)· patent assignee history
2020Based in Hsinchu, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG CO LTD452015–2020
GOEL SANDEEP KUMARself222012–2018
TAIWAN SEMICONDUCTOR MFG192013–2016
MEHTA ASHOK52013–2018
JOHN STANLEY42013–2018
Locations
LocationPatentsSpan
Dublin, California, US422013–2020
San Jose, California, US192013–2018
Eindhoven, NL32006–2015
Milpitas, California, US32012–2013
Hsinchu, TW22020