Inventor

Paul D. Madland

Inventor

Beaverton, OR, US

Overview

1976–2007

Patent span

Physics

Primary field (CPC G)

Patents· 29 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing63%

G11CStatic stores16%

H03KPulse technique13%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses6%

G01RMeasuring electric variables3%

PatentTitleYear

7,282,975'Apparatus and method to control self-timed and synchronous systems'2007 7,042,259'Adaptive frequency clock generation system'2006 6,737,880'Device and method for probing instantaneous high-speed local supply voltage fluctuation in VLSI integrated circuits using IR emissions'2004 6,573,755'Symmetric differential domino AND gate'2003 6,377,078'Circuit to reduce charge sharing for domino circuits with pulsed clocks'2002 6,378,062'Method and apparatus for performing a store operation'2002 5,881,262'Method and apparatus for blocking execution of and storing load operations during their execution'1999 5,860,154'Method and apparatus for calculating effective memory addresses'1999 5,844,852'Memory arrays with integrated bit line voltage stabilization circuitry'1998 5,826,109'Method and apparatus for performing multiple load operations to the same memory location in a computer system'1998 5,751,983'Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations'1998 5,748,937'Computer system that maintains processor ordering consistency by snooping an external bus for conflicts during out of order execution of memory access instructions'1998 5,724,536'Method and apparatus for blocking execution of and storing load operations during their execution'1998 5,717,882'Method and apparatus for dispatching and executing a load operation to memory'1998 5,694,574'Method and apparatus for performing load operations in a computer system'1997 5,680,572'Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers'1997 5,671,444'Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers'1997 5,664,137'Method and apparatus for executing and dispatching store operations in a computer system'1997 5,606,670'Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system'1997 5,588,126'Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system'1996 5,577,200'Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system'1996 5,532,636'Source-switched charge pump circuit'1996 5,526,510'Method and apparatus for implementing a single clock cycle line replacement in a data cache unit'1996 5,434,987'Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store'1995 5,031,141'Apparatus for generating self-timing for on-chip cache'1991 5,018,111'Timing circuit for memory employing reset function'1991 4,926,387'Memory timing circuit employing scaled-down models of bit lines using reduced number of memory cells'1990 4,727,518'Apparatus for limiting minority carrier injection in CMOS memories'1988 3,986,044'Clocked IGFET voltage level sustaining circuit'1976

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1976Patents assigned to MOTOROLA INC (1)· patent assignee history

1976Based in Tempe, AZ, US· patent location history

1988–2007Patents assigned to INTEL CORP (26)· patent assignee history

1988–2007Based in Beaverton, OR, US· patent location history

1996Based in Beverton, OR, US· patent location history

1997Patents assigned to INTEL CORPORAITON (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	26	1988–2007
INTEL CORPORAITON	1	1997
MOTOROLA INC	1	1976

Locations

Location	Patents	Span
Beaverton, OR, US	27	1988–2007
Beverton, OR, US	1	1996
Tempe, AZ, US	1	1976