Inventor
Nikil Dutt
Inventor
Irvine, CA, US
Overview
Patents· 7 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing71%
H03KPulse technique29%
PatentTitleYear
9,240,786'Homogeneous dual-rail logic for DPA attack resistive secure circuit design'20168,621,444'Retargetable instruction set simulators'20138,395,408'Homogeneous dual-rail logic for DPA attack resistive secure circuit design'20138,166,467'Automatic identification of application-specific functional units with architecturally visible storage'20127,778,815'Method for the fast exploration of bus-based communication architectures at the cycle-count-accurate-at-transaction-boundaries (CCATB) abstraction'20107,533,294'Functional coverage driven test generation for validation of pipelined processors'20097,383,529'Method and apparatus for designing circuits using high-level synthesis'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2016Patents assigned to UNIV CALIFORNIA (6)· patent assignee history
2008–2016Based in Irvine, CA, US· patent location history
2012–2016Patents assigned to DUTT NIKIL (4)· patent assignee history
2012Patents assigned to BISWAS PARTHA (1)· patent assignee history
2012Patents assigned to ECOLE POLYTECH (1)· patent assignee history
2013–2016Patents assigned to TANIMURA KAZUYUKI (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNIV CALIFORNIA | 6 | 2008–2016 |
| DUTT NIKILself | 4 | 2012–2016 |
| TANIMURA KAZUYUKI | 2 | 2013–2016 |
| BISWAS PARTHA | 1 | 2012 |
| ECOLE POLYTECH | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Irvine, California, US | 7 | 2008–2016 |