Inventor
Trevor Nigel Mudge
Inventor
Ann Arbor, MI, US
Overview
Patents· 44 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing49%
G11CStatic stores20%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use18%
H03KPulse technique7%
G06VImage or video recognition or understanding2%
H04LTransmission of digital information, e.g. telegraphic communication2%
Y04SSystems integrating technologies related to power network operation, communication or information technologies for improving the electrical power generation, transmission, distribution, management or usage, i.e. smart grids1%
PatentTitleYear
10,585,701Dynamically allocating storage elements to provide registers for processing thread groups202010,579,463Error recovery within integrated circuit202010,572,334Error recovery within integrated circuit202010,409,615Configurable arithmetic unit201910,037,295Apparatus and methods for generating a selection signal to perform an arbitration in a single cycle between multiple signal inputs having respective data to send201810,002,657Enhanced memory device20189,880,843'Data processing apparatus and method for decoding program instructions in order to generate control signals for processing circuitry of the data processing apparatus'20189,513,959'Contention management for a hardware transactional memory'20169,514,074'Single cycle arbitration within an interconnect'20169,471,480'Data processing apparatus with memory rename table for mapping memory addresses to registers'20169,448,875'Error recovery within integrated circuit'20169,164,842'Error recovery within integrated circuit'20159,135,011'Next branch table for use with a branch predictor'20158,868,817'Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry'20148,650,470'Error recovery within integrated circuit'20148,549,207'Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry'20138,407,537'Error recover within processing stages of an integrated circuit'20138,381,155'Vertical interconnect patterns in multi-layer integrated circuits'20138,346,832'Random number generator'20138,335,122'Cache memory system for a data processing apparatus'20128,285,936'Cache memory with power saving state'20128,255,610'Crossbar circuitry for applying a pre-selection prior to arbitration between transmission requests and method of operation of such crossbar circuitry'20128,230,152'Crossbar circuitry and method of operation of such crossbar circuitry'20128,230,277'Storage of data in data stores having some faulty storage locations'20128,185,786'Error recovery within processing stages of an integrated circuit'20128,145,960'Storage of data in data stores having some faulty storage locations'20128,108,585'Crossbar circuitry and method of operation of such crossbar circuitry'20127,701,240'Integrated circuit with error correction mechanisms to offset narrow tolerancing'20107,650,551'Error detection and recovery within processing stages of an integrated circuit'20107,533,226'Data processor memory circuit'20097,512,820'Performance level selection in a data processing system by combining a plurality of performance requests'20097,337,356'Systematic and random error detection and recovery within processing stages of an integrated circuit'20087,321,942'Performance counter for adding variable work increment value that is dependent upon clock frequency'20087,310,755'Data retention latch provision within integrated circuits'20077,278,080'Error detection and recovery within processing stages of an integrated circuit'20077,260,694'Data processor memory circuit'20077,194,385'Performance level setting of a data processing system'20077,162,661'Systematic and random error detection and recovery within processing stages of an integrated circuit'20077,131,015'Performance level selection in a data processing system using a plurality of performance request calculating algorithms'20067,072,229'Memory system having fast and slow data reading mechanisms'20067,055,007'Data processor memory circuit'20066,944,067'Memory system having fast and slow data reading mechanisms'20054,510,616'Design rule checking using serial neighborhood processors'19854,441,207'Design rule checking using serial neighborhood processors'1984Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1984–2015Patents assigned to UNIV MICHIGAN (31)· patent assignee history
1984–2020Based in Ann Arbor, MI, US· patent location history
2005–2020Patents assigned to ADVANCED RISC MACH LTD (18)· patent assignee history
2012–2016Patents assigned to MUDGE TREVOR NIGEL (15)· patent assignee history
2012–2014Patents assigned to BLAAUW DAVID THEODORE (10)· patent assignee history
2016–2020Patents assigned to UNIV MICHIGAN REGENTS (11)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNIV MICHIGAN | 31 | 1984–2015 |
| ADVANCED RISC MACH LTD | 18 | 2005–2020 |
| MUDGE TREVOR NIGELself | 15 | 2012–2016 |
| UNIV MICHIGAN REGENTS | 11 | 2016–2020 |
| BLAAUW DAVID THEODORE | 10 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Ann Arbor, MI, US | 44 | 1984–2020 |