Inventor
Tetsuhiko Okada
Inventor
Hachioji, JP
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing83%
C01FCompounds of the metals beryllium, magnesium, aluminium, calcium, strontium, barium, radium, thorium, or of the rare-earth metals4%
C08FMacromolecular compounds obtained by reactions only involving carbon-to-carbon unsaturated bonds4%
C08KUse of inorganic or non-macromolecular organic substances as compounding ingredients4%
C08LCompositions of macromolecular compounds4%
PatentTitleYear
10,920,039Flame-retardant resin composition and flame-retardant resin molded article2021RE041589'Memory system performing fast access to a memory location by omitting the transfer of a redundant address'20106,728,258'Multi-processor system and its network'20046,591,325'Method and apparatus of out-of-order transaction processing using request side queue pointer and response side queue pointer'20036,516,391'Multiprocessor system and methods for transmitting memory access transactions for the same'20036,389,518'Multiprocessor system and methods for transmitting memory access transactions for the same'20026,292,867'Data processing system'20016,219,735'Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement'20016,154,807'Memory system performing fast access to a memory location by omitting the transfer of a redundant address'20006,047,345'Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment'20006,011,791'Multi-processor system and its network'20005,873,122'Memory system performing fast access to a memory location by omitting transfer of a redundant address'19995,774,679'Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement'19985,678,062'Input/output control method and data processor'19975,657,458'Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment'19975,652,858'Method for prefetching pointer-type data structure and information processing apparatus therefor'19975,604,874'Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment'19975,590,290'Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement'19965,428,753'Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment'19955,408,625'Microprocessor capable of decoding two instructions in parallel'19955,220,670'Microprocessor having ability to carry out logical operation on internal bus'19935,148,532'Pipeline processor with prefetch circuit'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2004Patents assigned to HITACHI LTD (19)· patent assignee history
1992Based in Fuchu, JP· patent location history
1993–1995Based in Tama, JP· patent location history
1995–2010Based in Hachioji, JP· patent location history
1997Based in Hachiouji, JP· patent location history
2010Patents assigned to RENESAS TECH CORP (1)· patent assignee history
2021Patents assigned to TOYO STYRENE CO LTD (1)· patent assignee history
2021Based in Ichihara, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HITACHI LTD | 19 | 1992–2004 |
| RENESAS TECH CORP | 1 | 2010 |
| TOYO STYRENE CO LTD | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hachioji, JP | 17 | 1995–2010 |
| Tama, JP | 2 | 1993–1995 |
| Ichihara, JP | 1 | 2021 |
| Hachiouji, JP | 1 | 1997 |
| Fuchu, JP | 1 | 1992 |