Inventor
Huaqiang Wu
Inventor
Mountain View, CA, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices27%
H10DInorganic electric semiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
G11CStatic stores6%
H01LSemiconductor devices6%
C30BSingle-crystal growth5%
C01BNon-metallic elements3%
C01PIndexing scheme relating to structural and physical aspects of solid inorganic compounds3%
C23CCoating metallic material2%
G06FElectric digital data processing2%
PatentTitleYear
10,804,465Resistive random access memory and manufacturing method thereof202010,475,512Operation method of resistive random access memory and resistive random access memory device201910,468,099Circuit structure and driving method thereof, chip and authentication method thereof, and electronic device20199,712,124'Distributed amplifier'20179,659,733'Method for preparing a molybdenum disulfide film used in a field emission device'20179,455,352'HTO offset for long leffective, better device performance'20169,245,895'Oro and orpro with bit line trench to suppress transport program disturb'20168,653,581'HTO offset for long Leffective, better device performance'20148,549,608'Implement method and device of terminal call firewall'20138,455,268'Gate replacement with top oxide regrowth for the top oxide improvement'20138,330,209'HTO offset and BL trench process for memory device to improve device performance'20128,329,598'Sacrificial nitride and gate replacement'20128,039,891'Split charge storage node outer spacer process'20118,012,830'ORO and ORPRO with bit line trench to suppress transport program disturb'20117,981,745'Sacrificial nitride and gate replacement'20117,943,983'HTO offset spacers and dip off process to define junction'20117,935,596'HTO offset and BL trench process for memory device to improve device performance'20117,906,807'Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics'20117,883,963'Split charge storage node outer spacer process'20117,867,335'GaN bulk growth by Ga vapor transport'20117,829,936'Split charge storage node inner spacer process'20107,807,580'Triple poly-si replacement scheme for memory devices'20107,776,688'Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics'20107,772,288'Group III nitride coatings and methods'20107,569,206'Group III nitride compositions'20097,381,391'Method of making Group III nitrides'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2011Patents assigned to CORNELL RES FOUNDATION INC (4)· patent assignee history
2008–2016Based in Mountain View, CA, US· patent location history
2010–2014Patents assigned to SPANSION LLC (14)· patent assignee history
2011–2016Based in Burlingame, CA, US· patent location history
2011Based in Sunnyvale, CA, US· patent location history
2012–2016Patents assigned to WU HUAQIANG (6)· patent assignee history
2012–2016Patents assigned to CHANG KUO-TUNG (3)· patent assignee history
2013Based in Shenzhen, CN· patent location history
2017–2020Patents assigned to UNIV TSINGHUA (5)· patent assignee history
2017–2020Based in Beijing, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SPANSION LLC | 14 | 2010–2014 |
| WU HUAQIANGself | 6 | 2012–2016 |
| UNIV TSINGHUA | 5 | 2017–2020 |
| CORNELL RES FOUNDATION INC | 4 | 2008–2011 |
| CHANG KUO-TUNG | 3 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Mountain View, California, US | 14 | 2008–2016 |
| Beijing, CN | 5 | 2017–2020 |
| Burlingame, California, US | 5 | 2011–2016 |
| Shenzhen, CN | 1 | 2013 |
| Sunnyvale, California, US | 1 | 2011 |