Inventor
Benjamin Tsien
Inventor
Fremont, CA, US
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing56%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use27%
G11CStatic stores5%
H04LTransmission of digital information, e.g. telegraphic communication5%
G01RMeasuring electric variables2%
H03KPulse technique2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
PatentTitleYear
11,054,887System-wide low power management202110,884,477Coordinating accesses of shared resources by clients in a computing device202110,861,504Dynamic control of multi-region fabric202010,712,800Aligning active and idle phases in a mixed workload computing platform202010,671,148Multi-node system low power management202010,656,696Reducing chiplet wakeup latency202010,474,211Method for dynamic arbitration of real-time streams in the multi-client systems201910,403,351Save and restore scoreboard201910,340,916Using islands to control operating parameters for functional blocks in an electronic device201910,304,506Dynamic clock control to increase stutter efficiency in the memory subsystem201910,223,280Input/output memory map unit and northbridge201910,146,282System and method for monitoring and controlling a performance state change201810,025,721Input/output memory map unit and northbridge20189,870,473'System and method for security processor control over CPU power states'20189,396,360'System and method for secure control over performance state'20168,996,816'Method and apparatus for selectively bypassing a cache for trace collection in a processor'20158,732,410'Method and apparatus for accelerated shared data migration'20148,595,563'Method and circuitry for debugging a power-gated circuit'20138,255,636'Two-hop source snoop based messaging protocol'20128,041,774'Early issue of transaction ID'20117,991,964'Pre-coherence channel'20117,953,936'Hiding conflict, coherence completion and transaction ID elements of a coherence protocol'20117,814,292'Memory attribute speculation'20107,769,956'Pre-coherence channel'20107,640,401'Remote hit predictor'20097,620,694'Early issue of transaction ID'20097,546,421'Interconnect transaction translation technique'20097,543,115'Two-hop source snoop based cache coherence protocol'20097,512,741'Two-hop source snoop based messaging protocol'20097,437,518'Hiding conflict, coherence completion and transaction ID elements of a coherence protocol'20087,406,566'Ring interconnect with multiple coherence networks'20087,406,568'Buffer allocation for split data messages'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2012Patents assigned to INTEL CORP (13)· patent assignee history
2008–2021Based in Fremont, CA, US· patent location history
2009–2021Patents assigned to ADVANCED MICRO DEVICES INC (19)· patent assignee history
2012–2015Patents assigned to TSIEN BENJAMIN (4)· patent assignee history
2012Based in San Jose, CA, US· patent location history
2013–2015Patents assigned to HUGHES WILLIAM A (3)· patent assignee history
2018–2020Patents assigned to ATI TECHNOLOGIES ULC (5)· patent assignee history
2019Based in Santa Clara, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 19 | 2009–2021 |
| INTEL CORP | 13 | 2008–2012 |
| ATI TECHNOLOGIES ULC | 5 | 2018–2020 |
| TSIEN BENJAMINself | 4 | 2012–2015 |
| HUGHES WILLIAM A | 3 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 30 | 2008–2021 |
| Santa Clara, California, US | 1 | 2019 |
| San Jose, California, US | 1 | 2012 |