LexDanaLexDanabeta
Inventor

Ramesh Panwar

Inventor
Santa Clara, CA, US

Overview

77→
Patents
1998–2020
Patent span
Physics
Primary field (CPC G)

Patents· 77 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing62%
H04LTransmission of digital information, e.g. telegraphic communication31%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes2%
G11CStatic stores1%
PatentTitleYear
10,699,310Network router having service card20209,413,660'Methods and apparatus to implement except condition during data packet classification'20169,083,628'Content service aggregation system'20159,021,582'Parallelized pattern matching using non-deterministic finite automata'20158,804,950'Methods and apparatus for producing a hash value based on a hash function'20148,798,057'Methods and apparatus to implement except condition during data packet classification'20148,675,648'Methods and apparatus for compression in packet classification'20148,571,034'Methods and apparatus related to packet classification associated with a multi-stage switch'20138,571,023'Methods and Apparatus Related to Packet Classification Based on Range Values'20138,488,588'Methods and apparatus for indexing set bit values in a long vector associated with a switch fabric'20138,468,271'Providing privacy within computer networks using anonymous cookies'20138,370,528'Content service aggregation system'20138,139,591'Methods and apparatus for range matching during packet classification based on a linked-node structure'20128,111,697'Methods and apparatus for packet classification based on multiple conditions'20127,966,442'Cache using perfect hash function'20117,961,734'Methods and apparatus related to packet classification associated with a multi-stage switch'20117,889,741'Methods and apparatus for packet classification based on multiple conditions'20117,877,549'Enforcement of cache coherency policies using process synchronization services'20117,835,357'Methods and apparatus for packet classification based on policy vectors'20107,796,541'Methods and apparatus for range matching during packet classification based on a linked-node structure'20107,765,328'Content service aggregation system'20107,743,200'Instruction cache using perfect hash function'20107,738,454'Methods and apparatus related to packet classification based on range values'20107,363,353'Content service aggregation device for a data center'20087,305,492'Content service aggregation system'20076,920,542'Application processing employing a coprocessor'20056,901,482'Managing ownership of a full cache line using a store-create operation'20056,898,673'Co-processor including a media access controller'20056,895,477'Ring-based memory requests in a shared memory multi-processor'20056,892,282'Ring based multi-processing system'20056,880,049'Sharing a second tier cache memory in a multi-processor'20056,745,289'Processing packets in cache memory'20046,289,441'Method and apparatus for performing multiple branch predictions per cycle'20016,256,729'Method and apparatus for resolving multiple branches'20016,256,709'Method for storing data in two-way set associative odd and even banks of a cache memory'20016,240,502'Apparatus for dynamically reconfiguring a processor'20016,219,723'Method and apparatus for moderating current demand in an integrated circuit processor'20016,219,778'Apparatus for generating out-of-order results and out-of-order condition codes in a processor'20016,154,812'Method for inhibiting thrashing in a multi-level non-blocking cache system'20006,148,371'Multi-level non-blocking cache system with inhibiting thrashing'20006,144,982'Pipeline processor and computing system including an apparatus for tracking pipeline resources'20006,105,128'Method and apparatus for dispatching instructions to execution units in waves'20006,098,165'Fetching and handling a bundle of instructions comprising instructions and non-complex instructions'20006,094,719'Reducing data dependent conflicts by converting single precision instructions into microinstructions using renamed phantom registers in a processor having double precision registers'20006,085,305'Apparatus for precise architectural update in an out-of-order processor'20006,081,873'In-line bank conflict detection and resolution in a multi-ported non-blocking cache'20006,075,931'Method for efficient implementation of multi-ported logic FIFO structures in a processor'20006,058,472'Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine'20006,058,466'System for allocation of execution resources amongst multiple executing processes'20006,055,616'System for efficient implementation of multi-ported logic FIFO structures in a processor'20006,052,775'Method for non-intrusive cache fills and handling of load misses'20006,052,777'Method for delivering precise traps and interrupts in an out-of-order processor'20006,049,868'Apparatus for delivering precise traps and interrupts in an out-of-order processor'20006,035,374'Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency'20006,006,326'Apparatus for restraining over-eager load boosting in an out-of-order machine using a memory disambiguation buffer for determining dependencies'19995,999,727'Method for restraining over-eager load boosting using a dependency color indicator stored in cache with both the load and store instructions'19995,987,594'Apparatus for executing coded dependent instructions having variable latencies'19995,978,898'Allocating registers in a superscalar machine'19995,978,864'Method for thermal overload detection and prevention for an intergrated circuit processor'19995,964,869'Instruction fetch mechanism with simultaneous prediction of control-flow instructions'19995,958,047'Method for precise architectural update in an out-of-order processor'19995,948,106'System for thermal overload detection and prevention for an integrated circuit processor'19995,941,977'Apparatus for handling register windows in an out-of-order processor'19995,941,985'Branch instruction prediction method'19995,935,238'Selection from multiple fetch addresses generated concurrently including predicted and actual target by control-flow instructions in current and previous instruction bundles'19995,930,819'Method for performing in-line bank conflict detection and resolution in a multi-ported non-blocking cache'19995,898,853'Apparatus for enforcing true dependencies in an out-of-order processor'19995,890,008'Method for dynamically reconfiguring a processor'19995,884,070'Method for processing single precision arithmetic operations in system where two single precision registers are aliased to one double precision register'19995,880,978'Method and apparatus for creating an output vector from an input vector'19995,875,316'Method for handling complex instructions in an out-of-order processor'19995,870,597'Method for speculative calculation of physical register addresses in an out of order processor'19995,860,018'Method for tracking pipeline resources in a superscalar processor'19995,857,098'Branch instruction prediction apparatus'19995,854,761'Cache memory array which stores two-way set associative data'19985,850,533'Method for enforcing true dependencies in an out-of-order processor'19985,838,988'Computer product for precise architectural update in an out-of-order processor'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2001Patents assigned to SUN MICROSYSTEMS INC (41)· patent assignee history
1998–2001Based in Santa Clara, CA, US· patent location history
1999–2020Based in Pleasanton, CA, US· patent location history
2000Based in Sunnyvale, CA, US· patent location history
2004–2020Patents assigned to JUNIPER NETWORKS INC (32)· patent assignee history
2012–2015Patents assigned to PANWAR RAMESH (11)· patent assignee history
2012–2014Patents assigned to GOEL DEEPAK (6)· patent assignee history
2012–2014Patents assigned to JAGANNADHAN SRINIVASAN (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SUN MICROSYSTEMS INC411998–2001
JUNIPER NETWORKS INC322004–2020
PANWAR RAMESHself112012–2015
GOEL DEEPAK62012–2014
JAGANNADHAN SRINIVASAN52012–2014
Locations
LocationPatentsSpan
Santa Clara, California, US421998–2001
Pleasanton, California, US331999–2020
Sunnyvale, California, US22000