Inventor
Charles W. Koburger, III
Inventor
Delmar, NY, US
Overview
Patents· 220 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices23%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H01LSemiconductor devices8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
B82YSpecific uses or applications of nanostructures6%
H10BElectronic memory devices5%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
H10KOrganic electric solid-state devices2%
G11CStatic stores2%
PatentTitleYear
10,134,631Size-filtered multimetal structures201810,032,773FinFET with reduced capacitance20189,947,763FinFET with reduced capacitance20189,941,385Finfet with reduced capacitance20189,660,030'Replacement gate electrode with a self-aligned dielectric spacer'20179,627,377'Self-aligned dielectric isolation for FinFET devices'20179,620,619'Borderless contact structure'20179,536,979'FinFET with reduced capacitance'20179,496,356'Under-spacer doping in fin-based semiconductor devices'20169,484,254'Size-filtered multimetal structures'20169,455,323'Under-spacer doping in fin-based semiconductor devices'20169,379,198'Integrated circuit structure having selectively formed metal cap'20169,368,590'Silicon-on-insulator transistor with self-aligned borderless source/drain contacts'20169,312,275'FinFET with reduced capacitance'20169,269,621'Dual damascene dual alignment interconnect scheme'20169,263,290'Sub-lithographic semiconductor structures with non-constant pitch'20169,263,388'Overlay-tolerant via mask and reactive ion etch (RIE) technique'20169,202,879'Mask free protection of work function material portions in wide replacement gate electrodes'20159,196,613'Stress inducing contact metal in FinFET CMOS'20159,177,820'Sub-lithographic semiconductor structures with non-constant pitch'20159,141,749'Interconnect structures and methods for back end of the line integration'20159,105,641'Profile control in interconnect structures'20159,059,254'Overlay-tolerant via mask and reactive ion etch (RIE) technique'20159,040,363'FinFET with reduced capacitance'20158,946,908'Dual-metal self-aligned wires and vias'20158,946,866'Microelectronic substrate having removable edge extension element'20158,941,156'Self-aligned dielectric isolation for FinFET devices'20158,941,179'Finfets and fin isolation structures'20158,933,559'Carbon nanotube structures for enhancement of thermal dissipation from semiconductor modules'20158,928,091'Field-effect-transistor with self-aligned diffusion contact'20158,912,627'Electrical fuse structure and method of fabricating same'20148,906,807'Single fin cut employing angled processing methods'20148,901,744'Hybrid copper interconnect structure and method of fabricating same'20148,896,067'Method of forming finFET of variable channel width'20148,877,615'Methods of manufacturing finFET devices'20148,877,645'Integrated circuit structure having selectively formed metal cap'20148,871,624'Sealed air gap for semiconductor chip'20148,846,486'Deep well structures with single depth shallow trench isolation regions'20148,847,323'finFET devices'20148,836,031'Electrical isolation structures for ultra-thin semiconductor-on-insulator devices'20148,835,305'Method of fabricating a profile control in interconnect structures'20148,828,876'Dual mandrel sidewall image transfer processes'20148,828,862'Air-dielectric for subtractive etch line and via metallization'20148,803,321'Dual damascene dual alignment interconnect scheme'20148,796,783'Borderless contact structure employing dual etch stop layers'20148,785,284'FinFETs and fin isolation structures'20148,765,585'Method of forming a borderless contact structure employing dual etch stop layers'20148,754,483'Low-profile local interconnect and method of making the same'20148,735,279'Air-dielectric for subtractive etch line and via metallization'20148,716,127'Metal alloy cap integration'20148,704,343'Borderless interconnect line structure self-aligned to upper and lower level contact vias'20148,697,561'Microelectronic structure by selective deposition'20148,637,400'Interconnect structures and methods for back end of the line integration'20148,637,358'Field-effect-transistor with self-aligned diffusion contact'20148,629,008'Electrical isolation structures for ultra-thin semiconductor-on-insulator devices'20148,629,511'Mask free protection of work function material portions in wide replacement gate electrodes'20148,623,730'Method for fabricating silicon-on-insulator transistor with self-aligned borderless source/drain contacts'20148,609,534'Electrical fuse structure and method of fabricating same'20138,568,604'CMOS gate structures fabricated by selective oxidation'20138,569,168'Dual-metal self-aligned wires and vias'20138,541,823'Field effect transistor'20138,525,339'Hybrid copper interconnect structure and method of fabricating same'20138,492,270'Structure for nano-scale metallization and method for fabricating same'20138,492,274'Metal alloy cap integration'20138,471,343'Parasitic capacitance reduction in MOSFET by airgap ild'20138,450,806'Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby'20138,390,079'Sealed air gap for semiconductor chip'20138,368,146'FinFET devices'20138,349,674'Forming borderless contact for transistors in a replacement metal gate process'20138,300,452'Structure and method for improving storage latch susceptibility to single event upsets'20128,299,605'Carbon nanotube structures for enhancement of thermal dissipation from semiconductor modules'20128,299,625'Borderless interconnect line structure self-aligned to upper and lower level contact vias'20128,232,204'Method of forming borderless contact for transistor'20128,232,618'Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approach'20128,202,460'Microelectronic substrate having removable edge extension element'20128,198,700'Deep well structures with single depth shallow trench isolation regions'20128,183,159'Device component forming method with a trim step prior to sidewall image transfer (SIT) processing'20128,138,100'Microelectronic structure by selective deposition'20128,124,525'Method of forming self-aligned local interconnect and structure formed thereby'20128,039,334'Shared gate for conventional planar device and horizontal CNT'20118,030,202'Temporary etchable liner for forming air gap'20118,009,268'Immersion optical lithography system having protective optical coating'20118,004,024'Field effect transistor'20117,994,575'Metal-oxide-semiconductor device structures with tailored dopant depth profiles'20117,989,222'Method of making integrated circuit chip utilizing oriented carbon nanotube conductive layers'20117,985,643'Semiconductor transistors with contact holes close to gates'20117,965,540'Structure and method for improving storage latch susceptibility to single event upsets'20117,951,660'Methods for fabricating a metal-oxide-semiconductor device structure'20117,936,017'Reduced floating body effect without impact on performance-enhancing stress'20117,932,167'Phase change memory cell with vertical transistor'20117,932,549'Carbon nanotube conductor for trench capacitors'20117,923,202'Layer patterning using double exposure processes in a single photoresist layer'20117,898,045'Passive electrically testable acceleration and voltage measurement devices'20117,851,064'Methods and structures for promoting stable synthesis of carbon nanotubes'20107,838,943'Shared gate for conventional planar device and horizontal CNT'20107,834,384'Simultaneous conditioning of a plurality of memory cells through series resistors'20107,829,883'Vertical carbon nanotube field effect transistors and arrays'20107,825,525'Layout and process to contact sub-lithographic structures'20107,820,502'Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby'20107,816,743'Microelectronic structure by selective deposition'20107,791,145'Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures'20107,786,583'Integrated circuit chip utilizing oriented carbon nanotube conductive layers'20107,771,604'Reduced mask count gate conductor definition'20107,750,406'Design structure incorporating a hybrid substrate'20107,737,504'Well isolation trenches (WIT) for CMOS devices'20107,727,848'Methods and semiconductor structures for latch-up suppression using a conductive region'20107,704,855'Method for fabricating strained silicon-on-insulator structures and strained silicon-on-insulator structures formed thereby'20107,699,996'Sidewall image transfer processes for forming multiple line-widths'20107,691,720'Vertical nanotube semiconductor device structures and methods of forming the same'20107,674,674'Method of forming a dual gated FinFET gain cell'20107,668,004'Non-volatile switching and memory devices using vertical nanotubes'20107,659,171'Methods and structure for forming self-aligned borderless contacts for strain engineered logic devices'20107,655,985'Methods and semiconductor structures for latch-up suppression using a conductive region'20107,651,902'Hybrid substrates and methods for forming such hybrid substrates'20107,652,334'Shallow trench isolation formation'20107,648,869'Method of fabricating semiconductor structures for latch-up suppression'20107,646,469'Immersion optical lithography system having protective optical coating'20107,645,676'Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures'20107,629,192'Passive electrically testable acceleration and voltage measurement devices'20097,607,455'Micro-electro-mechanical valves and pumps and methods of fabricating same'20097,601,205'Carbon nanotubes as low voltage field emission sources for particle precipitators'20097,585,614'Sub-lithographic imaging techniques and processes'20097,579,272'Methods of forming low-k dielectric layers containing carbon nanostructures'20097,566,613'Method of forming a dual gated FinFET gain cell'20097,560,347'Methods for forming a wrap-around gate field effect transistor'20097,557,023'Implantation of gate regions in semiconductor device fabrication'20097,541,608'Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells'20097,535,016'Vertical carbon nanotube transistor integration'20097,528,494'Accessible chip stack and process of manufacturing thereof'20097,525,156'Shallow trench isolation fill by liquid phase deposition of SiO2'20097,521,808'Wiring paterns formed by selective metal plating'20097,521,776'Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers'20097,521,735'Multiple layer and crystal plane orientation semiconductor substrate'20097,517,716'Method of forming optical sensor that includes three pairs of electrodes formed at different depths in a semiconductor substrate'20097,510,939'Microelectronic structure by selective deposition'20097,504,314'Method for fabricating oxygen-implanted silicon on insulation type semiconductor and semiconductor formed therefrom'20097,505,110'Micro-electro-mechanical valves and pumps'20097,495,743'Immersion optical lithography system having protective optical coating'20097,491,618'Methods and semiconductor structures for latch-up suppression using a conductive region'20097,492,046'Electric fuses using CNTs (carbon nanotubes)'20097,491,631'Method of doping a gate electrode of a field effect transistor'20097,483,285'Memory devices using carbon nanotube (CNT) technologies'20097,473,633'Method for making integrated circuit chip having carbon nanotube composite interconnection vias'20097,439,144'CMOS gate structures fabricated by selective oxidation'20087,435,653'Methods for forming a wrap-around gate field effect transistor'20087,402,194'Carbon nanotubes as low voltage field emission sources for particle precipitators'20087,397,692'High performance single event upset hardened SRAM cell'20087,393,779'Shrinking contact apertures through LPD oxide'20087,387,974'Methods for providing gate conductors on semiconductors and semiconductors formed thereby'20087,385,275'Shallow trench isolation method for shielding trapped charge in a semiconductor device'20087,385,839'Memory devices using carbon nanotube (CNT) technologies'20087,381,655'Mandrel/trim alignment in SIT processing'20087,381,610'Semiconductor transistors with contact holes close to gates'20087,378,717'Semiconductor optical sensors'20087,378,678'Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells'20087,374,793'Methods and structures for promoting stable synthesis of carbon nanotubes'20087,368,712'Y-shaped carbon nanotubes as AFM probe for analyzing substrates with angled topography'20087,358,140'Pattern density control using edge printing processes'20087,358,120'Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM'20087,352,607'Non-volatile switching and memory devices using vertical nanotubes'20087,351,666'Layout and process to contact sub-lithographic structures'20087,351,648'Methods for forming uniform lithographic features'20087,352,030'Semiconductor devices with buried isolation regions'20087,348,634'Shallow trench isolation formation'20087,348,610'Multiple layer and crystal plane orientation semiconductor substrate'20087,345,370'Wiring patterns formed by selective metal plating'20087,335,930'Borderless contact structures'20087,329,613'Structure and method for forming semiconductor wiring levels using atomic layer deposition'20087,276,768'Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures'20077,273,794'Shallow trench isolation fill by liquid phase deposition of SiO2'20077,271,878'Wafer cell for immersion lithography'20077,271,079'Method of doping a gate electrode of a field effect transistor'20077,271,444'Wrap-around gate field effect transistor'20077,268,028'Well isolation trenches (WIT) for CMOS devices'20077,265,013'Sidewall image transfer (SIT) technologies'20077,264,415'Methods of forming alternating phase shift masks having improved phase-shift tolerance'20077,256,114'Process for oxide cap formation in semiconductor manufacturing'20077,256,415'Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells'20077,250,347'Double-gate FETs (Field Effect Transistors)'20077,233,063'Borderless contact structures'20077,233,071'Low-k dielectric layer based upon carbon nanostructures'20077,230,681'Method and apparatus for immersion lithography'20077,229,889'Methods for metal plating of gate conductors and semiconductors formed thereby'20077,229,909'Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes'20077,227,233'Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM'20077,135,773'Integrated circuit chip utilizing carbon nanotube composite interconnection vias'20067,129,097'Integrated circuit chip utilizing oriented carbon nanotube conductive layers'20067,109,546'Horizontal memory gain cells'20067,102,201'Strained semiconductor device structures'20067,088,422'Moving lens for immersion optical lithography'20067,087,531'Shallow trench isolation formation'20067,084,060'Forming capping layer over metal wire structure using selective atomic layer deposition'20067,074,666'Borderless contact structures'20067,071,047'Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions'20067,038,299'Selective synthesis of semiconducting carbon nanotubes'20067,026,259'Liquid-filled balloons for immersion lithography'20067,027,125'System and apparatus for photolithography'20066,998,204'Alternating phase mask built by additive film deposition'20066,989,308'Method of forming FinFET gates without long etches'20066,989,323'Method for forming narrow gate structures on sidewalls of a lithographically defined sacrificial material'20066,970,372'Dual gated finfet gain cell'20056,890,828'Method for supporting a bond pad in a multilevel interconnect structure and support structure formed thereby'20056,875,685'Method of forming gas dielectric with support structure'20056,875,703'Method for forming quadruple density sidewall image transfer (SIT) structures'20056,713,835'Method for manufacturing a multi-level interconnect structure'20046,531,375'Method of forming a body contact using BOX modification'20036,503,813'Method and structure for forming a trench in a semiconductor substrate'20036,498,096'Borderless contact to diffusion with respect to gate conductor and methods for fabricating'20026,294,449'Self-aligned contact for closely spaced transistors'20016,215,190'Borderless contact to diffusion with respect to gate conductor and methods for fabricating'20015,894,169'Low-leakage borderless contacts to doped regions'19995,605,862'Process for making low-leakage contacts'19975,545,581'Plug strap process utilizing selective nitride and oxide etches'19965,173,439'Forming wide dielectric-filled isolation trenches in semi-conductors'19925,006,482'Forming wide dielectric-filled planarized isolation trenches in semiconductors'19914,944,682'Method of forming borderless contacts'19904,799,990'Method of self-aligning a trench isolation structure to an implanted well region'19894,558,508'Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step'19854,556,585'Vertically isolated complementary transistors'19854,389,257'Fabrication method for high conductivity, void-free polysilicon-silicide integrated circuit electrodes'1983Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1983–2018Patents assigned to IBM (209)· patent assignee history
1983–1985Based in Underhill, VT, US· patent location history
1989–2003Based in Essex, VT, US· patent location history
1996–2006Based in Essex Junction, VT, US· patent location history
2005–2018Based in Delmar, NY, US· patent location history
2012–2017Patents assigned to KOBURGER III CHARLES W (37)· patent assignee history
2012–2017Patents assigned to HORAK DAVID V (33)· patent assignee history
2012–2017Patents assigned to PONOTH SHOM (21)· patent assignee history
2012–2017Patents assigned to YANG CHIH-CHAO (19)· patent assignee history
2012–2014Based in Albany, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 209 | 1983–2018 |
| KOBURGER III CHARLES Wself | 37 | 2012–2017 |
| HORAK DAVID V | 33 | 2012–2017 |
| PONOTH SHOM | 21 | 2012–2017 |
| YANG CHIH-CHAO | 19 | 2012–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Delmar, New York, US | 195 | 2005–2018 |
| Essex Junction, VT, US | 8 | 1996–2006 |
| Albany, New York, US | 6 | 2012–2014 |
| Essex, VT, US | 5 | 1989–2003 |
| Underhill, VT, US | 3 | 1983–1985 |