Inventor
ALEKSANDAR ALEKSOV
Inventor
US
Overview
Patents· 127 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices30%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1030%
H10DInorganic electric semiconductor devices8%
H05KPrinted circuits7%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
H01PWaveguides5%
H01QAntennas, i.e. radio aerials3%
H03HImpedance networks, e.g. resonant circuits2%
H01FMagnets2%
H01GCapacitors1%
PatentTitleYear
12,598,997Inductor with integrated magnetics202612,573,744Wideband antennas in glass through direct via feeding and glass stacking202612,550,768Conformal power delivery structures near high-speed signal traces202612,542,358Microelectronic devices designed with mold patterning to create package-level components for high frequency communication systems202612,525,496Glass vias and planes with reduced tapering202612,520,506In situ inductor structure in buildup power planes202612,519,073Conformal power delivery structures of 3D stacked die assemblies202612,512,396Flexible die to floor planning with bump pitch scale through glass core via pitch202512,494,443Substrate integrated thin film capacitors using amorphous high-k dielectrics202512,489,032Cooling of conformal power delivery structures202512,476,175Glass substrates having transverse capacitors for use with semiconductor packages and related methods202512,456,702Device, method and system to mitigate stress on hybrid bonds in a multi-tier arrangement of chiplets202512,456,705First layer interconnect first on carrier approach for EMIB patch202512,444,619Physical vapor deposition seeding for high aspect ratio vias in glass core technology202512,444,672Hybrid bonding technologies with thermal expansion compensation structures202512,438,087High throughput additive manufacturing for integrated circuit components containing traces with feature size and grain boundaries202512,431,430Technologies for high throughput additive manufacturing for integrated circuit components202512,424,716RF filters and multiplexers manufactured in the core of a package substrate using glass core technology202512,424,719Compact surface transmission line waveguides with vertical ground planes202512,381,182Direct bonding in microelectronic assemblies202512,368,091Package substrate with glass core having vertical power planes for improved power delivery202512,354,992First layer interconnect first on carrier approach for EMIB patch202512,349,282Capacitors in through glass vias202512,347,761Magnetic planar spiral and high aspect ratio inductors for power delivery in the glass-core of a package substrate202512,327,775Thermal performance in hybrid bonded 3D die stacks202512,288,751Microelectronic assemblies202512,266,682Capacitors and resistors at direct bonding interfaces in microelectronic assemblies202512,261,097Thermal management in integrated circuit packages202512,255,130Airgap structures for high speed signal integrity202512,255,225Low leakage thin film capacitors using titanium oxide dielectric with conducting noble metal oxide electrodes202512,242,290Integrating voltage regulators and passive circuit elements with top side power planes in stacked die architectures202512,218,069Multi-chip package with high density interconnects202512,205,902High-density interconnects for integrated circuit packages202512,199,018Direct bonding in microelectronic assemblies202512,183,961Methods for conductively coating millimeter waveguides202412,176,323Microelectronic assemblies202412,176,223Integrated circuit package supports202412,165,962Hermetic sealing structures in microelectronic assemblies having direct bonding202412,165,994Radio frequency antennas and waveguides for communication between integrated circuit devices202412,155,133Microelectronic devices designed with mold patterning to create package-level components for high frequency communication systems202412,155,372Multi-filter die202412,150,271Platforms including microelectronic packages therein coupled to a chassis, where waveguides couple the microelectronic packages to each other and usable in a computing device202412,142,510Carrier for microelectronic assemblies having direct bonding202412,136,596Microelectronic assemblies202412,113,026Multi-chip package and method of providing die-to-die interconnects in same202412,107,060Microelectronic assemblies with inductors in direct bonding regions202412,062,631Microelectronic assemblies with inductors in direct bonding regions202412,057,402Direct bonding in microelectronic assemblies202412,040,776Integrated radio frequency (RF) front-end module (FEM)202412,027,466Conductive route patterning for electronic substrates202412,007,170Thermal management in integrated circuit packages202412,002,745High performance integrated RF passives using dual lithography process202411,990,448Direct bonding in microelectronic assemblies202411,942,334Microelectronic assemblies having conductive structures with different thicknesses202411,935,857Surface finishes with low RBTV for fine and mixed bump pitch architectures202411,908,802Multi-chip package with high density interconnects202411,894,324In-package RF waveguides as high bandwidth chip-to-chip interconnects and methods for using the same202411,876,053Multi-chip package and method of providing die-to-die interconnects in same202411,854,834Integrated circuit package supports202311,837,534Substrate with variable height conductive and dielectric elements202311,830,831Semiconductor package including a modular side radiating waveguide launcher202311,830,787Thermal management in integrated circuit packages202311,824,008Multi-chip package and method of providing die-to-die interconnects in same202311,804,455Substrate integrated thin film capacitors using amorphous high-k dielectrics202311,791,528Low loss and low cross talk transmission lines with stacked dielectric layers for forming stubs of different thickness or for forming a coaxial line202311,784,108Thermal management in integrated circuit packages202311,784,181Die backend diodes for electrostatic discharge (ESD) protection202311,769,734Microelectronic assemblies202311,756,948In situ package integrated thin film capacitors for power delivery202311,751,367Microelectronic package electrostatic discharge (ESD) protection202311,728,258Electroless metal-defined thin pad first level interconnects for lithographically defined vias202311,728,290Waveguide fan-out202311,721,650Method for fabricating multiplexed hollow waveguides of variable type on a semiconductor package202311,716,826Platforms including microelectronic packages therein coupled to a chassis, where waveguides couple the microelectronic packages to each other and usable in a computing device202311,715,693Dielectric waveguide channel for interconnecting dies in a semiconductor package usable in a computing device and method of manufacture202311,694,951Zero-misalignment two-via structures202311,694,962Microelectronic package with mold-integrated components202311,688,660Bridge for radio frequency (RF) multi-chip modules202311,676,918Electrostatic discharge protection in integrated circuits202311,664,303Interconnection structure fabrication using grayscale lithography202311,658,418Microelectronic devices designed with mold patterning to create package-level components for high frequency communication systems202311,641,711Microelectronic package with substrate-integrated components202311,621,236Electrostatic discharge protection in integrated circuits using positive temperature coefficient material202311,621,192Inorganic dies with organic interconnect layers and related structures202311,605,603Microelectronic package with radio frequency (RF) chiplet202311,605,867Fabricating an RF filter on a semiconductor package using selective seeding202311,538,803Integration of III-V transistors in a silicon CMOS stack202211,532,574Through-substrate waveguide202211,532,584Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling202211,502,037Zero-misalignment two-via structures using photoimageable dielectric, buildup film, and electrolytic plating202211,495,552Substrate integrated thin film capacitors using amorphous high-k dielectrics202211,488,918Surface finishes with low rBTV for fine and mixed bump pitch architectures202211,460,499Dual sided thermal management solutions for integrated circuit packages202211,462,480Microelectronic assemblies having interposers202211,437,706Package with side-radiating wave launcher and waveguide202211,430,751Microelectronic devices designed with 3D stacked ultra thin package modules for high frequency communications202211,421,376Inorganic piezoelectric materials formed on fibers and applications thereof202211,424,239Diodes for package substrate electrostatic discharge (ESD) protection202211,393,766Multi-chip package with high density interconnects202211,394,094Waveguide connector having a curved array of waveguides configured to connect a package to excitation elements202211,387,187Embedded very high density (VHD) layer202211,360,512Electronic device fabric integration202211,348,897Microelectronic assemblies202211,348,882Package spark gap structure202211,335,641Microelectronic assemblies202211,329,358Low loss and low cross talk transmission lines having l-shaped cross sections202211,328,986Capacitor-wirebond pad structures for integrated circuit packages202211,328,996Zero-misalignment two-via structures using photoimageable dielectric film buildup film, and transparent substrate with electroless plating202211,316,497Multi-filter die202211,309,619Waveguide coupling systems and methods202211,309,192Integrated circuit package supports202211,310,907Microelectronic package with substrate-integrated components202211,296,040Electrostatic discharge protection in integrated circuits202211,289,431Electrostatic discharge protection in integrated circuits using materials with optically controlled electrical conductivity202211,264,307Dual-damascene zero-misalignment-via process for semiconductor packaging202211,264,373Die backend diodes for electrostatic discharge (ESD) protection202211,264,239Polarization defined zero misalignment vias for semiconductor packaging202211,257,745Electroless metal-defined thin pad first level interconnects for lithographically defined vias202211,244,912Semiconductor package having a coaxial first layer interconnect202211,239,155Conductive contact structures for electrostatic discharge protection in integrated circuits202211,227,825High performance integrated RF passives using dual lithography process202211,222,856Package-integrated bistable switch for electrostatic discharge (ESD) protection202211,222,836Zero-misalignment two-via structures202211,211,345In-package RF waveguides as high bandwidth chip-to-chip interconnects and methods for using the same202111,189,580Electrostatic discharge protection in integrated circuits202111,158,917Dual-substrate waveguide filter202111,147,197Microelectronic package electrostatic discharge (ESD) protection2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (127)· patent assignee history
2021–2026Based in US· patent location history
2022Patents assigned to INTEL COROPRATION (1)· patent assignee history
2024Patents assigned to INTEL CORPROATION (1)· patent assignee history
2026Patents assigned to INTE CORP (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 127 | 2021–2026 |
| INTE CORP | 1 | 2026 |
| INTEL COROPRATION | 1 | 2022 |
| INTEL CORPROATION | 1 | 2024 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 127 | 2021–2026 |