Inventor

Kevin F. Reick

Inventor

Round Rock, TX, US

Overview

1998–2019

Patent span

Physics

Primary field (CPC G)

Patents· 51 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing86%

G01RMeasuring electric variables5%

H04LTransmission of digital information, e.g. telegraphic communication4%

G11CStatic stores2%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

PatentTitleYear

10,509,457Adaptive frequency optimization in processors2019 9,720,703'Data driven hardware chips initialization via hardware procedure framework'2017 9,720,704'Data driven hardware chips initialization via hardware procedure framework'2017 9,251,076'Epoch-based recovery for coherent attached processor proxy'2016 9,021,211'Epoch-based recovery for coherent attached processor proxy'2015 8,650,431'Non-disruptive hardware change'2014 8,443,313'Circuit design optimization'2013 8,386,230'Circuit design optimization'2013 8,291,259'Delete of cache line with correctable error'2012 8,285,939'Lateral castout target selection'2012 8,271,738'Apparatus for operating cache-inhibited memory mapped commands to access registers'2012 8,176,355'Recovery from hardware access errors'2012 8,090,823'Providing low-level hardware access to in-band and out-of-band firmware'2012 7,916,722'Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor'2011 7,765,362'Efficient system bootstrap loading'2010 7,574,581'Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled components'2009 7,467,204'Method for providing low-level hardware access to in-band and out-of-band firmware'2008 7,418,541'Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor'2008 7,392,350'Method to operate cache-inhibited memory mapped commands to access registers'2008 7,386,678'Efficient system bootstrap loading'2008 7,117,126'Data processing system and method with dynamic idle for tunable interface calibration'2006 7,117,388'Dynamic, Non-invasive detection of hot-pluggable problem components and re-active re-allocation of system resources from problem components'2006 7,089,462'Early clock fault detection method and circuit for detecting clock faults in a multiprocessing system'2006 7,080,288'Method and apparatus for interface failure survivability using error correction'2006 7,055,003'Data cache scrub mechanism for large L2/L3 data cache structures'2006 7,055,002'Integrated purge store mechanism to flush L2/L3 cache structure for improved reliabity and serviceability'2006 7,007,210'Method and system for handling multiple bit errors to enhance system reliability'2006 6,990,545'Non-disruptive, dynamic hot-plug and hot-remove of server nodes in an SMP'2006 6,832,342'Method and apparatus for reducing hardware scan dump data'2004 6,802,031'Method and apparatus for increasing the effectiveness of system debug and analysis'2004 6,745,321'Method and apparatus for harvesting problematic code sections aggravating hardware design flaws in a microprocessor'2004 6,662,133'JTAG-based software to perform cumulative array repair'2003 6,654,917'Method and apparatus for scanning free-running logic'2003 6,643,796'Method and apparatus for providing cooperative fault recovery between a processor and a service processor'2003 6,633,838'Multi-state logic analyzer integral to a microprocessor'2003 6,631,463'Method and apparatus for patching problematic instructions in a microprocessor using software interrupts'2003 6,629,170'Method and apparatus for a byte lane selectable performance monitor bus'2003 6,629,268'Method and apparatus for servicing a processing system through a test port'2003 6,587,963'Method for performing hierarchical hang detection in a computer system'2003 6,550,020'Method and system for dynamically configuring a central processing unit with multiple processing cores'2003 6,543,003'Method and apparatus for multi-stage hang recovery in an out-of-order microprocessor'2003 6,543,002'Recovery from hang condition in a microprocessor'2003 6,539,500'System and method for tracing'2003 6,529,979'Method and apparatus for a high-speed serial communications bus protocol with positive acknowledgement'2003 6,446,029'Method and system for providing temporal threshold support during performance monitoring of a pipelined processor'2002 6,438,722'Method and system for testing an integrated circuit'2002 6,415,378'Method and system for tracking the progress of an instruction in an out-of-order processor'2002 6,393,594'Method and system for performing pseudo-random testing of an integrated circuit'2002 6,333,653'System and method for phase alignment of a plurality of clock pulses when starting, stopping and pulsing clocks'2001 6,321,380'Method and apparatus for modifying instruction operations in a processor'2001 5,802,350'System and method for selecting an interrupt system based upon the operating system of a multiprocessor system'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2019Patents assigned to IBM (51)· patent assignee history

1998Based in Pleasant Valley, NY, US· patent location history

2001–2006Based in Austin, TX, US· patent location history

2006–2019Based in Round Rock, TX, US· patent location history

2012–2014Patents assigned to REICK KEVIN F (6)· patent assignee history

2012Patents assigned to FIELDS JR JAMES STEPHEN (2)· patent assignee history

2012Patents assigned to GUTHRIE GUY L (2)· patent assignee history

2012Patents assigned to HELTERHOFF HARMONY L (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	51	1998–2019
REICK KEVIN Fself	6	2012–2014
FIELDS JR JAMES STEPHEN	2	2012
GUTHRIE GUY L	2	2012
HELTERHOFF HARMONY L	2	2012

Locations

Location	Patents	Span
Round Rock, Texas, US	26	2006–2019
Austin, Texas, US	24	2001–2006
Pleasant Valley, New York, US	1	1998