Inventor
Helia Naeimi
Inventor
Santa Clara, CA, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing37%
G11CStatic stores34%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use8%
B82YSpecific uses or applications of nanostructures3%
H02JElectric power networks3%
H02KDynamo-electric machines3%
H02NElectric machines not otherwise provided for3%
H03KPulse technique3%
H03MCoding3%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
PatentTitleYear
10,713,052Prefetcher for delinquent irregular loads202010,552,257Adaptive error correction in memory devices202010,467,137Apparatus, system, integrated circuit die, and method to determine when to bypass a second level cache when evicting modified data from a first level cache201910,423,540Apparatus, system, and method to determine a cache line in a first memory device to be evicted for an incoming cache line from a second memory device201910,304,510Destructive reads from spin transfer torque memory under read-write conditions201910,297,302Magnetic storage cell memory with back hop-prevention201910,061,376Opportunistic power management for managing intermittent power available to data processing device having semi-non-volatile memory or non-volatile memory20189,978,432Write operations in spin transfer torque memory20189,892,775'Destructive reads from spin transfer torque memory under read-write conditions'20189,858,984'Apparatuses, methods, and systems for increasing a speed of removal of data from a memory cell'20189,747,967'Magnetic field-assisted memory operation'20179,703,626'Recycling error bits in floating point units'20179,589,620'Destructive reads from spin transfer torque memory under read-write conditions'20179,558,807'Apparatuses and systems for increasing a speed of removal of data stored in a memory cell'20179,520,192'Resistive memory write operation with merged reset'20169,514,796'Magnetic storage cell memory with back hop-prevention'20169,342,403'Method and apparatus for managing a spin transfer torque memory'20169,335,996'Recycling error bits in floating point units'20169,299,412'Write operations in spin transfer torque memory'20169,223,544'Number representation and memory system for arithmetic'20158,316,283'Hybrid error correction code (ECC) for a processor'20128,134,341'Energy harvesting based on user-interface of mobile computing device'20127,242,601'Deterministic addressing of nanoscale devices assembled at sublithographic pitches'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007Patents assigned to CALIFORNIA INST OF TECHN (1)· patent assignee history
2007Based in Pasadena, CA, US· patent location history
2012–2020Patents assigned to INTEL CORP (22)· patent assignee history
2012–2016Patents assigned to NAEIMI HELIA (4)· patent assignee history
2012–2020Based in Santa Clara, CA, US· patent location history
2015–2016Patents assigned to LU SHIH-LIEN L (2)· patent assignee history
2016Patents assigned to AUGUSTINE CHARLES (1)· patent assignee history
2016–2018Based in Sunnyvale, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 22 | 2012–2020 |
| NAEIMI HELIAself | 4 | 2012–2016 |
| LU SHIH-LIEN L | 2 | 2015–2016 |
| AUGUSTINE CHARLES | 1 | 2016 |
| CALIFORNIA INST OF TECHN | 1 | 2007 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 19 | 2012–2020 |
| Sunnyvale, California, US | 3 | 2016–2018 |
| Pasadena, California, US | 1 | 2007 |