Inventor
Edward R. Prack
Inventor
Phoenix, AZ, US
Overview
Patents· 35 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1039%
H01LSemiconductor devices24%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
Y10TTechnical subjects covered by former us classification5%
C09JAdhesives4%
C08GMacromolecular compounds obtained otherwise than by reactions only involving unsaturated carbon-to-carbon bonds2%
C08LCompositions of macromolecular compounds2%
C09DCoating compositions, e.g. paints, varnishes or lacquers2%
B23KSoldering or unsoldering1%
PatentTitleYear
10,930,634Integrated circuit system and packaging method therefor202110,867,959Integrated circuit packaging method and integrated packaged circuit202010,615,151Integrated circuit multichip stacked packaging structure and method202010,573,622Methods of forming joint structures for surface mount packages202010,128,225Interconnect structures with polymer core201810,068,863Formation of solder and copper interconnect structures and associated techniques and configurations201810,049,971Package structure to enhance yield of TMI interconnections20189,859,248'Laser die backside film removal for integrated circuit (IC) packaging'20189,824,991'Organic thin film passivation of metal interconnections'20179,786,517'Ablation method and recipe for wafer level underfill material patterning and removal'20179,659,889'Solder-on-die using water-soluble resist system and method'20179,613,933'Package structure to enhance yield of TMI interconnections'20179,613,934'Interconnect structures with polymer core'20179,583,390'Organic thin film passivation of metal interconnections'20179,508,667'Formation of solder and copper interconnect structures and associated techniques and configurations'20169,472,517'Dry-removable protective coatings'20169,412,702'Laser die backside film removal for integrated circuit (IC) packaging'20169,257,276'Organic thin film passivation of metal interconnections'20169,165,914'Forming die backside coating structures with coreless packages'20158,987,918'Interconnect structures with polymer core'20158,674,519'Microelectronic package and method of manufacturing same'20148,466,559'Forming die backside coating structures with coreless packages'20138,404,519'Process that includes assembling together first and second substrates the have respective first and second carbon nanotube arrays with geometrically complementary patterns'20138,072,062'Circuit device with at least partial packaging and method for forming'20117,971,347'Method of interconnecting workpieces'20117,964,447'Process of making carbon nanotube array that includes impregnating the carbon nanotube array with metal'20117,545,030'Article having metal impregnated within carbon nanotube array'20097,462,551'Adhesive system for supporting thin silicon wafer'20087,428,138'Forming carbon nanotube capacitors'20087,361,987'Circuit device with at least partial packaging and method for forming'20086,921,975'Circuit device with at least partial packaging, exposed active surface and a voltage reference plane'20056,888,246'Semiconductor power device with shear stress compensation'20056,838,776'Circuit device with at least partial packaging and method for forming'20056,664,200'Method of manufacturing a semiconductor component and polyimide etchant therefor'20036,646,347'Semiconductor power device and method of formation'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2011Based in Austin, TX, US· patent location history
2005–2011Patents assigned to FREESCALE SEMICONDUCTOR INC (5)· patent assignee history
2008–2020Patents assigned to INTEL CORP (25)· patent assignee history
2008–2021Based in Phoenix, AZ, US· patent location history
2011–2017Patents assigned to PRACK EDWARD R (7)· patent assignee history
2016–2017Patents assigned to FARUQUI DANISH (2)· patent assignee history
2020–2021Patents assigned to SHENZHEN XIUYUAN ELECTRONIC TECH CO LTD (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 25 | 2008–2020 |
| PRACK EDWARD Rself | 7 | 2011–2017 |
| FREESCALE SEMICONDUCTOR INC | 5 | 2005–2011 |
| SHENZHEN XIUYUAN ELECTRONIC TECH CO LTD | 3 | 2020–2021 |
| FARUQUI DANISH | 2 | 2016–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Phoenix, AZ, US | 28 | 2008–2021 |
| Austin, Texas, US | 7 | 2003–2011 |