Inventor
Uk-Rae Cho
Inventor
Suwon-si, KR
Overview
Patents· 48 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores33%
H03KPulse technique22%
H03HImpedance networks, e.g. resonant circuits7%
H10DInorganic electric semiconductor devices7%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses6%
H04LTransmission of digital information, e.g. telegraphic communication5%
G01RMeasuring electric variables4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
G06FElectric digital data processing2%
PatentTitleYear
9,537,470'Semiconductor device and method for operating the same'20179,318,607'Semiconductor device and method of fabricating the same'20169,130,550'Semiconductor device and method for operating the same'20158,578,227'Delay test device and system-on-chip having the same'20138,531,208'Flip-flop and semiconductor device including the same'20137,924,604'Stacked memory cell for use in high-density CMOS SRAM'20117,825,710'Delay-locked loop circuits and method for generating transmission core clock signals'20107,697,314'Data line layout and line driving method in semiconductor memory device'20107,656,723'Semiconductor memory device with hierarchical bit line structure'20107,616,512'Semiconductor memory device with hierarchical bit line structure'20097,551,013'Phase interpolation circuit and method of generating phase interpolation signal'20097,548,086'Impedance control circuit in semiconductor device and impedance control method'20097,525,173'Layout structure of MOS transistors on an active region'20097,489,570'Semiconductor memory device with hierarchical bit line structure'20097,471,109'Output impedance circuit and output buffer circuit including the same'20087,454,672'Semiconductor memory device testable with a single data rate and/or dual data rate pattern in a merged data input/output pin test mode'20087,400,177'Amplifier circuit having constant output swing range and stable delay time'20087,385,414'Impedance controllable ouput drive circuit in semiconductor device and impedance control method therefor'20087,307,441'Integrated circuit chips and wafers including on-chip test element group circuits, and methods of fabricating and testing same'20077,295,489'Method and circuit for writing double data rate (DDR) sampled data in a memory device'20077,274,580'Content addressable memory device'20077,187,214'Amplifier circuit having constant output swing range and stable delay time'20077,170,318'Impedance controller and impedance control method'20077,154,312'Apparatus for generating internal clock signal'20067,016,257'Semiconductor memory device capable of generating variable clock signals according to modes of operation'20067,002,822'Content addressable memory device'20066,992,514'Synchronous mirror delay circuit and semiconductor integrated circuit device having the same'20066,947,336'Semiconductor device with impedance control circuit'20056,930,508'Integrated circuit with on-chip termination'20056,901,014'Circuits and methods for screening for defective memory cells in semiconductor memory devices'20056,839,286'Semiconductor device with programmable impedance control circuit'20056,815,230'Control signal transmitting method with package power pin and related integrated circuit package structure'20046,785,173'Semiconductor memory device capable of performing high-frequency wafer test operation'20046,661,250'Programmable impedance control circuit'20036,642,740'Programmable termination circuit and method'20036,628,155'Internal clock generating circuit of semiconductor memory device and method thereof'20036,617,894'Circuits and methods for generating internal clock signal of intermediate phase relative to external clock'20036,594,818'Memory architecture permitting selection of storage density after fabrication of active circuitry'20036,583,647'Signal converting system having level converter for use in high speed semiconductor device and method therefor'20036,573,746'Impedance control circuit'20036,556,038'Impedance updating apparatus of termination circuit and impedance updating method thereof'20036,525,558'Programmable impedance control circuit'20036,456,124'Method and apparatus for controlling impedance of an off-chip driver circuit'20026,429,679'Programmable impedance control circuit and method thereof'20025,680,062'Gunn transceiver logic input circuit for use in a semiconductor memory device'19975,173,760'BiCMOS semiconductor device'19924,970,174'Method for making a BiCMOS semiconductor device'19904,912,055'Method of fabricating a semiconductor device'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–2017Patents assigned to SAMSUNG ELECTRONICS CO LTD (47)· patent assignee history
1990Based in Kyoungsangbuk, KR· patent location history
1992–2007Based in Kyungki-do, KR· patent location history
2002–2017Based in Suwon-si, KR· patent location history
2003Based in Kyonggi-do, KR· patent location history
2007Based in Gyeonggi-do, KR· patent location history
2013Patents assigned to CHO UK RAE (1)· patent assignee history
2013Patents assigned to CHO UK-RAE (1)· patent assignee history
2013Patents assigned to JUNG GUN OK (1)· patent assignee history
2013Patents assigned to KIM MIN SU (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 47 | 1990–2017 |
| CHO UK RAEself | 1 | 2013 |
| CHO UK-RAEself | 1 | 2013 |
| JUNG GUN OK | 1 | 2013 |
| KIM MIN SU | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Suwon-si, KR | 40 | 2002–2017 |
| Kyungki-do, KR | 4 | 1992–2007 |
| Kyoungsangbuk, KR | 2 | 1990 |
| Gyeonggi-do, KR | 1 | 2007 |
| Kyonggi-do, KR | 1 | 2003 |