Inventor
Ranjan Khurana
Inventor
Boise, ID, US
Overview
Patents· 13 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1029%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1026%
H01LSemiconductor devices17%
H10DInorganic electric semiconductor devices12%
H10BElectronic memory devices10%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
PatentTitleYear
9,741,580'Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice pattern from an oblique lattice pattern, and methods of forming a pattern on a substrate'20179,583,381'Methods for forming semiconductor devices and semiconductor device structures'20179,460,998'Semiconductor constructions and methods of forming semiconductor constructions'20169,229,328'Methods of forming semiconductor device structures, and related semiconductor device structures'20168,999,852'Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice pattern from an oblique lattice pattern, and methods of forming a pattern on a substrate'20158,937,018'Methods of forming a pattern on a substrate'20158,889,559'Methods of forming a pattern on a substrate'20148,889,558'Methods of forming a pattern on a substrate'20148,796,086'Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate'20148,741,781'Methods of forming semiconductor constructions'20148,586,429'Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate'20138,389,353'Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate'20138,039,340'Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011–2017Patents assigned to MICRON TECHNOLOGY INC (13)· patent assignee history
2011–2017Based in Boise, ID, US· patent location history
2013–2014Patents assigned to KHURANA RANJAN (3)· patent assignee history
2013Patents assigned to DAVIS NEAL L (2)· patent assignee history
2013Patents assigned to HOUSLEY RICHARD T (2)· patent assignee history
2014Patents assigned to DORHOUT JUSTIN B (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 13 | 2011–2017 |
| KHURANA RANJANself | 3 | 2013–2014 |
| DAVIS NEAL L | 2 | 2013 |
| HOUSLEY RICHARD T | 2 | 2013 |
| DORHOUT JUSTIN B | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 13 | 2011–2017 |