Inventor
Yen-Shih Ho
Inventor
Kaohsiung, TW
Overview
Patents· 82 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%
H01LSemiconductor devices22%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10DInorganic electric semiconductor devices10%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation8%
B81BMicrostructural devices or systems, e.g. micromechanical devices3%
G06VImage or video recognition or understanding3%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems2%
G06KGraphical data reading2%
G06FElectric digital data processing1%
PatentTitleYear
10,461,117Semiconductor structure and method for manufacturing semiconductor structure201910,424,540Chip package and method for forming the same201910,388,541Wafer coating system and method of manufacturing chip package201910,318,784Touch panel-sensing chip package module complex and a manufacturing method thereof201910,152,180Chip scale sensing chip package and a manufacturing method thereof201810,153,237Chip package and method for forming the same201810,109,559Electronic device package and fabrication method thereof201810,096,635Semiconductor structure and manufacturing method thereof201810,049,252Chip package and fabrication method thereof201810,050,006Chip package and method for forming the same20189,997,473Chip package and method for forming the same20189,978,788Photosensitive module and method for forming the same20189,947,716Chip package and manufacturing method thereof20189,887,229'Sensing chip package and a manufacturing method thereof'20189,881,889'Chip package and method for fabricating the same'20189,875,912Chip package and manufacturing method thereof20189,793,234'Chip package and manufacturing method thereof'20179,780,251'Semiconductor structure and manufacturing method thereof'20179,761,555'Passive component structure and manufacturing method thereof'20179,711,403'Method for forming chip package'20179,685,354'Separation apparatus and a method for separating a cap layer from a chip package by means of the separation apparatus'20179,653,422'Chip package and method for forming the same'20179,640,683'Electrical contact structure with a redistribution layer connected to a stud'20179,640,488'Chip package and method for forming the same'20179,633,935'Stacked chip package including substrate with recess adjoining side edge of substrate and method for forming the same'20179,611,143'Method for forming chip package'20179,613,904'Semiconductor structure and manufacturing method thereof'20179,601,460'Chip package including recess in side edge'20179,570,398'Chip package and method for forming the same'20179,548,265'Chip package and manufacturing method thereof'20179,450,015'Manufacturing method of semiconductor structure'20169,437,478'Chip package and method for forming the same'20169,425,134'Chip package'20169,419,050'Manufacturing method of semiconductor structure with protein tape'20169,406,590'Chip package and manufacturing method thereof'20169,373,597'Chip package and method thereof'20169,355,975'Chip package and method for forming the same'20169,334,156'Chip package and method thereof'20169,334,158'Chip package and method for forming the same'20169,331,024'IC wafer having electromagnetic shielding effects and method for making the same'20169,331,256'Semiconductor structure with sensor chip and landing pads'20169,305,843'Chip package and method for forming the same'20169,287,417'Semiconductor chip package and method for manufacturing thereof'20169,275,963'Semiconductor structure having stage difference surface and manufacturing method thereof'20169,275,958'Chip package and method for forming the same'20169,236,320'Chip package'20169,214,579'Electrical contact structure with a redistribution layer connected to a stud'20159,177,862'Semiconductor stack structure and fabrication method thereof'20159,165,890'Chip package comprising alignment mark and method for forming the same'20159,153,528'Chip package and method for forming the same'20159,153,707'Chip package and method for forming the same'20159,136,241'Chip package and manufacturing method thereof'20159,054,114'Chip package structure and manufacturing method thereof'20159,024,437'Chip package and method for forming the same'20158,981,497'Chip package structure and method for forming the same'20158,975,755'Chip package'20158,963,312'Stacked chip package and method for forming the same'20158,928,098'Semiconductor package and fabrication method thereof'20158,900,924'Chip package and method for forming the same'20148,836,134'Semiconductor stacked package and method of fabricating the same'20148,779,452'Chip package'20148,779,558'Chip package structure and manufacturing method thereof'20148,692,300'Interposer and method for forming the same'20148,692,358'Image sensor chip package and method for forming the same'20148,674,518'Chip package and method for forming the same'20148,673,686'Chip package structure and manufacturing method thereof'20148,643,070'Chip package and method for forming the same'20148,624,362'IC wafer having electromagnetic shielding effects and method for making the same'20148,614,488'Chip package and method for forming the same'20138,409,925'Chip package structure and manufacturing method thereof'20137,592,891'Planar spiral inductor structure having enhanced Q value'20097,370,403'Method of fabricating a planar spiral inductor structure having an enhanced Q value'20087,294,544'Method of making a metal-insulator-metal capacitor in the CMOS process'20077,038,294'Planar spiral inductor structure with patterned microelectronic structure integral thereto'20066,881,996'Metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer'20056,812,088'Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer'20046,667,217'Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process'20036,472,721'Dual damascene interconnect structures that include radio frequency capacitors and inductors'20026,329,234'Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow'20016,096,629'Uniform sidewall profile etch method for forming low contact leakage schottky diode contact'20006,051,475'Method for manufacturing a silicide to silicide capacitor'20006,004,829'Method of increasing end point detection capability of reactive ion etching by adding pad area'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2009Patents assigned to TAIWAN SEMICONDUCTOR MFG (12)· patent assignee history
1999–2007Based in Chia Yi, TW· patent location history
2001–2009Based in Hsinchu, TW· patent location history
2004–2005Based in Kuei Shan Hsiang, TW· patent location history
2013–2017Patents assigned to HO YEN-SHIH (14)· patent assignee history
2013–2017Patents assigned to LIU TSANG-YU (9)· patent assignee history
2013–2014Patents assigned to CHANG SHU-MING (6)· patent assignee history
2013–2019Based in Kaohsiung, TW· patent location history
2014–2019Patents assigned to XINTEC INC (60)· patent assignee history
2014–2015Based in Jhubei City, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| XINTEC INC | 60 | 2014–2019 |
| HO YEN-SHIHself | 14 | 2013–2017 |
| TAIWAN SEMICONDUCTOR MFG | 12 | 1999–2009 |
| LIU TSANG-YU | 9 | 2013–2017 |
| CHANG SHU-MING | 6 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kaohsiung, TW | 66 | 2013–2019 |
| Hsinchu, TW | 5 | 2001–2009 |
| Jhubei City, TW | 4 | 2014–2015 |
| Chia Yi, TW | 4 | 1999–2007 |
| Kuei Shan Hsiang, TW | 2 | 2004–2005 |