Inventor

Stanislav V. Aleshin

Inventor

Moscow, RU

Overview

45→

Patents

1996–2013

Patent span

Electricity

Primary field (CPC H)

Patents· 45 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing22%

H10DInorganic electric semiconductor devices14%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%

G11CStatic stores12%

H03KPulse technique12%

H10BElectronic memory devices12%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices11%

G06TImage data processing or generation, in general2%

H04MTelephonic communication1%

Y02PClimate change mitigation technologies in the production or processing of goods1%

PatentTitleYear

8,515,055'Adaptive filtering with flexible selection of algorithm complexity and performance'2013 7,493,577'Automatic recognition of geometric points in a target IC design for OPC mask quality calculation'2009 7,406,675'Method and system for improving aerial image simulation speeds'2008 7,401,318'Method and apparatus for optimizing fragmentation of boundaries for optical proximity correction (OPC) purposes'2008 7,340,706'Method and system for analyzing the quality of an OPC mask'2008 7,260,814'OPC edge correction based on a smoothed mask design'2007 7,039,896'Gradient method of mask edge correction'2006 7,035,446'Quality measurement of an aerial image'2006 6,988,260'Method and apparatus for optimizing fragmentation of boundaries for optical proximity correction (OPC) purposes'2006 6,934,410'Mask correction for photolithographic processes'2005 6,911,285'Sidelobe correction for attenuated phase shift masks'2005 6,898,780'Method and system for constructing a hierarchy-driven chip covering for optical proximity correction'2005 6,854,104'First approximation for OPC significant speed-up'2005 6,813,758'Optical proximity correction driven hierarchy'2004 6,785,871'Automatic recognition of an optically periodic structure in an integrated circuit design'2004 6,407,434'Hexagonal architecture'2002 6,312,980'Programmable triangular shaped device having variable gain'2001 6,263,299'Geometric aerial image simulation'2001 6,197,456'Mask having an arbitrary complex transmission function'2001 6,134,702'Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints'2000 6,109,201'Resynthesis method for significant delay reduction'2000 6,097,073'Triangular semiconductor or gate'2000 5,973,376'Architecture having diamond shaped or parallelogram shaped cells'1999 5,909,376'Physical design automation system and process for designing integrated circuit chips using highly parallel sieve optimization with multiple \"jiggles\"'1999 5,889,329'Tri-directional interconnect architecture for SRAM'1999 5,872,380'Hexagonal sense cell architecture'1999 5,864,165'Triangular semiconductor NAND gate'1999 5,838,585'Physical design automation system and method using monotonically improving linear clusterization'1998 5,835,378'Computer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chip'1998 5,834,821'Triangular semiconductor \"AND\" gate device'1998 5,822,214'CAD for hexagonal architecture'1998 5,811,863'Transistors having dynamically adjustable characteristics'1998 5,808,330'Polydirectional non-orthoginal three layer interconnect architecture'1998 5,801,422'Hexagonal SRAM architecture'1998 5,789,770'Hexagonal architecture with triangular shaped cells'1998 5,784,287'Physical design automation system and process for designing integrated circuit chips using generalized assignment'1998 5,777,360'Hexagonal field programmable gate array architecture'1998 5,742,086'Hexagonal DRAM array'1998 5,712,793'Physical design automation system and process for designing integrated circuit chips using fuzzy cell clusterization'1998 5,699,265'Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints'1997 5,661,663'Physical design automation system and method using hierarchical clusterization and placement improvement based on complete re-placement of cell clusters'1997 5,654,563'Microelectronic integrated circuit including triangular semiconductor \"or\" g'1997 5,650,653'Microelectronic integrated circuit including triangular CMOS \"nand\" gate device'1997 5,631,581'Microelectronic integrated circuit including triangular semiconductor \"and\" gate device'1997 5,578,840'Microelectronic integrated circuit structure and method using three directional interconnect routing based on hexagonal geometry'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996Patents assigned to LIS LOGIC CORP (1)· patent assignee history

1996–2013Based in Moscow, RU· patent location history

1997–2008Patents assigned to LSI LOGIC CORP (39)· patent assignee history

2000Based in Moskow, SU· patent location history

2007–2013Patents assigned to LSI CORP (5)· patent assignee history

2013Patents assigned to ALESHIN STANISLAV VLADIMIROVICH (1)· patent assignee history

2013Patents assigned to BABIN DMITRY NIKOLAEVICH (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
LSI LOGIC CORP	39	1997–2008
LSI CORP	5	2007–2013
ALESHIN STANISLAV VLADIMIROVICHself	1	2013
BABIN DMITRY NIKOLAEVICH	1	2013
LIS LOGIC CORP	1	1996

Locations

Location	Patents	Span
Moscow, RU	44	1996–2013
Moskow, SU	1	2000