Inventor
Huai-Yuan Tseng
Inventor
San Ramon, CA, US
Overview
Patents· 47 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores51%
H10BElectronic memory devices14%
H01LSemiconductor devices10%
H10DInorganic electric semiconductor devices8%
G06FElectric digital data processing6%
G09GArrangements or circuits for control of indicating devices using static means to present variable information4%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein1%
H01JElectric discharge tubes or discharge lamps1%
H04NPictorial communication, e.g. television1%
H10KOrganic electric solid-state devices1%
PatentTitleYear
11,081,162Source side precharge and boosting improvement for reverse order program202111,081,180Memory device with bit lines disconnected from NAND strings for fast programming202111,081,184Method of concurrent multi-state programming of non-volatile memory with bit line voltage step up202111,062,780System and method of reading two pages in a nonvolatile memory202111,037,635Power management for multi-plane read operations202111,024,393Read operation for non-volatile memory with compensation for adjacent wordline202111,017,869Programming process combining adaptive verify with normal and slow programming speeds in a memory device202110,861,537Countermeasures for first read issue202010,839,922Memory disturb detection202010,832,778Negative voltage wordline methods and systems202010,811,089Adaptive programming voltage for non-volatile memory devices202010,734,070Programming selection devices in non-volatile memory strings202010,726,922Memory device with connected word lines for fast programming202010,726,891Reducing post-read disturb in a nonvolatile memory device202010,714,198Dynamic 1-tier scan for high performance 3D NAND202010,643,721Interleaved program and verify in non-volatile memory202010,643,692Adaptive programming voltage for non-volatile memory devices202010,636,494Apparatus and method for reducing noise generated from locked out sense circuits in a non-volatile memory system202010,636,487Memory device with bit lines disconnected from NAND strings for fast programming202010,614,898Adaptive control of memory cell programming voltage202010,559,370System and method for in-situ programming and read operation adjustments in a non-volatile memory202010,559,365Peak current suppression202010,541,038Subgroup selection for verification202010,535,412Single pulse verification of memory cells202010,482,985Dynamic erase loop dependent bias voltage201910,482,984Ramp down sensing between program voltage and verify voltage in memory device201910,468,111Asymmetric voltage ramp rate control201910,381,083Bit line control that reduces select gate transistor disturb in erase operations201910,229,744First read countermeasures in memory201910,157,680Sub-block mode for non-volatile memory201810,026,486First read countermeasures in memory201810,026,492Multi-die programming with die-jumping induced periodic delays201810,014,063Smart skip verify mode for programming a memory device20189,875,805Double lockout in non-volatile memory20189,721,672'Multi-die programming with die-jumping induced periodic delays'20179,711,211'Dynamic threshold voltage compaction for non-volatile memory'20179,570,179'Non-volatile memory with two phased programming'20179,548,130'Non-volatile memory with prior state sensing'20179,437,321'Error detection method'20169,343,164'Compensating source side resistance versus word line'20167,972,912'Method of fabricating semiconductor device'20117,605,783'Driving circuit of light emitting element'20097,532,182'Image display with photo sensor'20097,504,694'Structure of semiconductor device'20097,495,736'Pixel array with flexible circuit layout having respective scan and data line profiles with predetermined wave construction so as to evenly distribute any strain on the respective scan and data lines to withstand stress and be flexible'20097,259,029'Method of forming protective structure for active matrix triode field emission device'20076,958,492'Thin film transistor structure for a field emission display and the method for making the same'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2011Patents assigned to IND TECH RES INST (7)· patent assignee history
2007–2009Based in Pingzhen City, TW· patent location history
2009–2011Based in Taoyuan County, TW· patent location history
2016–2021Patents assigned to SANDISK TECHNOLOGIES LLC (38)· patent assignee history
2016–2018Patents assigned to SANDISK TECHNOLOGIES INC (8)· patent assignee history
2016–2021Based in San Ramon, CA, US· patent location history
2018Patents assigned to SANDISK TECH LLP (1)· patent assignee history
2019Based in Milpitas, CA, US· patent location history
2020–2021Based in San Jose, CA, US· patent location history
2021Patents assigned to SanDiskTechnologies LLC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK TECHNOLOGIES LLC | 38 | 2016–2021 |
| SANDISK TECHNOLOGIES INC | 8 | 2016–2018 |
| IND TECH RES INST | 7 | 2005–2011 |
| SANDISK TECH LLP | 1 | 2018 |
| SanDiskTechnologies LLC | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Ramon, California, US | 33 | 2016–2021 |
| San Jose, California, US | 6 | 2020–2021 |
| Pingzhen City, TW | 4 | 2007–2009 |
| Taoyuan County, TW | 2 | 2009–2011 |
| Milpitas, California, US | 1 | 2019 |