Inventor
Mario J. Interrante
Inventor
New Paltz, NY, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1033%
H05KPrinted circuits19%
B23KSoldering or unsoldering12%
Y02PClimate change mitigation technologies in the production or processing of goods10%
Y10TTechnical subjects covered by former us classification8%
H01LSemiconductor devices7%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
H01RElectrically-conductive connections2%
G02BOptical elements, systems or apparatus2%
B08BCleaning in general1%
PatentTitleYear
11,049,841Silicon interposer sandwich structure for ESD, EMC, and EMC shielding and protection202110,903,187Selective area heating for 3D chip stack202110,262,970Selective area heating for 3D chip stack20199,860,996'Selective area heating for 3D chip stack'20189,431,366'Selective area heating for 3D chip stack'20169,373,590'Integrated circuit bonding with interposer die'20169,224,712'3D bond and assembly process for severely bowed interposer die'20159,105,629'Selective area heating for 3D chip stack'20159,059,241'3D assembly for interposer bow'20158,689,437'Method for forming integrated circuit assembly'20148,614,512'Solder ball contact susceptible to lower stress'20138,487,447'Semiconductor structure having offset passivation to reduce electromigration'20138,383,505'Solder ball contact susceptible to lower stress'20137,781,232'Method to recover underfilled modules by selective removal of discrete components'20106,917,113'Lead-free alloys for column/ball grid arrays, organic interposers and passive component assembly'20056,892,925'Solder hierarchy for lead free solder joint'20056,854,636'Structure and method for lead free solder electronic package interconnections'20056,827,505'Optoelectronic package structure and process for planar passive optical and optoelectronic devices'20046,762,119'Method of preventing solder wetting in an optical device using diffusion of Cr'20046,740,959'EMI shielding for semiconductor chip carriers'20046,574,859'Interconnection process for module assembly and rework'20036,532,654'Method of forming an electrical connector'20036,518,674'Temporary attach article and method for temporary attach of devices to a substrate'20036,497,357'Apparatus and method for removing interconnections'20026,458,623'Conductive adhesive interconnection with insulating polymer carrier'20026,429,388'High density column grid array connections and method thereof'20026,360,938'Process and apparatus to remove closely spaced chips on a multi-chip module'20026,302,732'Coaxial connection apparatus and method of attachment'20016,303,400'Temporary attach article and method for temporary attach of devices to a substrate'20016,287,126'Mechanical attachment means used as electrical connection'20016,283,359'Method for enhancing fatigue life of ball grid arrays'20016,259,155'Polymer enhanced column grid array'20016,235,996'Interconnection structure and process module assembly and rework'20016,216,937'Process and apparatus to remove closely spaced chips on a multi-chip module'20016,158,644'Method for enhancing fatigue life of ball grid arrays'20006,037,193'Hermetic sealing of a substrate of high thermal conductivity using an interposer of low thermal conductivity'20005,990,418'Hermetic CBGA/CCGA structure with thermal paste cooling'19995,945,735'Hermetic sealing of a substrate of high thermal conductivity using an interposer of low thermal conductivity'19995,543,584'Structure for repairing electrical lines'19965,478,009'Selective removal of a single solder ball from an array of solder balls'19955,425,493'Selective addition of a solder ball to an array of solder balls'19955,288,007'Apparatus and methods for making simultaneous electrical connections'19945,243,140'Direct distribution repair and engineering change system'19935,193,732'Apparatus and methods for making simultaneous electrical connections'19935,153,408'Method and structure for repairing electrical lines'19924,634,638'High melting point copper-gold-tin brazing alloy for chip carriers'1987Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1987–2021Patents assigned to IBM (45)· patent assignee history
1987–2021Based in New Paltz, NY, US· patent location history
2013Patents assigned to INTERRANTE MARIO J (3)· patent assignee history
2013Patents assigned to SHAPIRO MICHAEL J (3)· patent assignee history
2013Patents assigned to GUERIN LUC (2)· patent assignee history
2013Patents assigned to TRAN-QUINN THUY (2)· patent assignee history
2015Based in Hopewell Junction, NY, US· patent location history
2021Based in Armonk, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 45 | 1987–2021 |
| INTERRANTE MARIO Jself | 3 | 2013 |
| SHAPIRO MICHAEL J | 3 | 2013 |
| GUERIN LUC | 2 | 2013 |
| TRAN-QUINN THUY | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| New Paltz, New York, US | 44 | 1987–2021 |
| Armonk, New York, US | 1 | 2021 |
| Hopewell Junction, New York, US | 1 | 2015 |