Inventor
Gregory J. Fredeman
Inventor
Wappingers Falls, NY, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores87%
G06FElectric digital data processing3%
G07CTime or attendance registers3%
H03KPulse technique3%
H10BElectronic memory devices3%
PatentTitleYear
11,081,202Failing address registers for built-in self tests202111,069,422Testing multi-port array in integrated circuits202110,943,647Bit-line mux driver with diode header for computer memory202110,930,339Voltage bitline high (VBLH) regulation for computer memory202110,832,756Negative voltage generation for computer memory20209,748,958'Dynamic high voltage driver with adjustable clamped output level'20179,053,770'Dynamic cascode-managed high-voltage word-line driver circuit'20159,047,930'Single-ended low-swing power-savings mechanism with process compensation'20159,025,403'Dynamic cascode-managed high-voltage word-line driver circuit'20157,817,455'Random access electrically programmable e-fuse ROM'20107,774,660'Flexible row redundancy system'20107,609,577'Design structure for improving sensing margin of electrically programmable fuses'20097,525,831'Method for improving sensing margin of electrically programmable fuses'20097,404,113'Flexible row redundancy system'20087,307,911'Apparatus and method for improving sensing margin of electrically programmable fuses'20077,270,269'Secure electronic voting device'20077,242,239'Programming and determining state of electrical fuse using field effect transistor having multiple conduction states'20077,194,670'Command multiplier for built-in-self-test'20077,093,171'Flexible row redundancy system'20067,085,180'Method and structure for enabling a redundancy allocation during a multi-bank operation'20067,046,572'Low power manager for standby operation of memory system'20067,023,758'Low power manager for standby operation of a memory system'20066,954,387'Dynamic random access memory with smart refresh scheduler'20056,768,143'Structure and method of making three finger folded field effect transistors having shared junctions'20046,674,673'Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture'20046,674,676'Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture'20046,542,973'Integrated redundancy architecture system for an embedded DRAM'20036,445,626'Column redundancy architecture system for an embedded DRAM'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2021Patents assigned to IBM (28)· patent assignee history
2002Based in Essex Junction, VT, US· patent location history
2003–2010Based in Staatsburg, NY, US· patent location history
2004Based in Staatsurg, NY, US· patent location history
2007–2021Based in Wappingers Falls, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 28 | 2002–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Wappingers Falls, New York, US | 15 | 2007–2021 |
| Staatsburg, New York, US | 10 | 2003–2010 |
| Staatsurg, New York, US | 2 | 2004 |
| Essex Junction, VT, US | 1 | 2002 |