Inventor
Lavanya Subramanian
Inventor
Santa Clara, CA, US
Overview
Patents· 4 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing57%
G11CStatic stores29%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use14%
PatentTitleYear
10,559,348System, apparatus and method for simultaneous read and precharge of a memory202010,191,689Systems and methods for page management using local page information201910,176,124Scoreboard approach to managing idle page close timeout duration in memory20199,921,839'Coordinated thread criticality-aware memory scheduling'2018Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2018–2020Patents assigned to INTEL CORP (4)· patent assignee history
2018Patents assigned to BASHYAM NITHIYANANDAN (1)· patent assignee history
2018Patents assigned to NORI ANANT (1)· patent assignee history
2018Patents assigned to SUBRAMANIAN LAVANYA (1)· patent assignee history
2018Patents assigned to SUBRAMONEY SREENIVAS (1)· patent assignee history
2018–2019Based in Santa Clara, CA, US· patent location history
2020Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 4 | 2018–2020 |
| BASHYAM NITHIYANANDAN | 1 | 2018 |
| NORI ANANT | 1 | 2018 |
| SUBRAMANIAN LAVANYAself | 1 | 2018 |
| SUBRAMONEY SREENIVAS | 1 | 2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 3 | 2018–2019 |
| San Jose, California, US | 1 | 2020 |