Inventor
Jui-Feng Kuan
Inventor
Zhubei City, TW
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing40%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H01LSemiconductor devices12%
H10DInorganic electric semiconductor devices7%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices5%
Y02PClimate change mitigation technologies in the production or processing of goods5%
G01RMeasuring electric variables3%
H10NElectric solid-state devices not otherwise provided for3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein2%
PatentTitleYear
10,943,052Integrated circuit design method, system and computer program product202110,910,365Structure and method for cooling three-dimensional integrated circuits202110,763,253Structure and method for cooling three-dimensional integrated circuits202010,719,652Electromigration sign-off tool202010,685,161Region based shrinking methodology for integrated circuit layout migration202010,634,972Configurable heating device and method of using the same202010,540,475System for manufacturing a semiconductor device202010,509,883Method for layout generation with constrained hypergraph partitioning201910,346,576Electromigration sign-off methodology201910,162,244Configurable heating device201810,163,787Semiconductor structure201810,157,252Method and apparatus of a three dimensional integrated circuit201810,095,827Method of manufacturing a semiconductor device201810,083,257Method, system and computer program product for generating simulation sample201810,042,967Electromigration sign-off methodology20189,996,643Integrated circuit modeling method using resistive capacitance information20189,934,352Method and system for manufacturing a semiconductor device20189,753,895'Method for process variation analysis of an integrated circuit'20179,748,228'Structure and method for cooling three-dimensional integrated circuits'20179,698,099'Semiconductor structure having a plurality of conductive paths'20179,519,735'Method of failure analysis'20169,418,200'Integrated circuit design system and method of generating proposed device array layout'20169,411,926'Method of performing circuit simulation and generating circuit layout'20169,367,654'Variation modeling'20169,355,205'Method and apparatus of a three dimensional integrated circuit'20169,348,965'Parasitic component library and method for efficient circuit design and simulation using the same'20169,213,797'Method, system and computer program product for designing semiconductor device'20159,129,082'Variation factor assignment'20159,122,833'Method of designing fin field effect transistor (FinFET)-based circuit and system for implementing the same'20159,092,589'Integrated circuit design flow with device array layout generation'20159,053,255'Semiconductor structure and method of generating masks for making integrated circuit'20158,943,454'In-phase grouping for voltage-dependent design rule'20158,893,066'Parasitic component library and method for efficient circuit design and simulation using the same'20148,856,701'Method of radio-frequency and microwave device generation'20148,769,476'Method of performing circuit simulation and generating circuit layout'20148,707,230'Method and system for semiconductor simulation'20148,701,055'Macro cell based process design kit for advanced applications'20148,621,409'System and method for reducing layout-dependent effects'20138,601,416'Method of circuit design yield analysis'20138,495,532'Systems and methods for creating frequency-dependent RC extraction netlist'20138,453,095'Systems and methods for creating frequency-dependent netlist'20138,252,489'Mask-shift-aware RC extraction for double patterning design'20126,903,644'Inductor device having improved quality factor'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (19)· patent assignee history
2005Based in Hsinchu, TW· patent location history
2012–2014Patents assigned to KUAN JUI-FENG (6)· patent assignee history
2012–2013Patents assigned to CHENG YI-KAN (5)· patent assignee history
2012–2013Patents assigned to CHAO HSIAO-SHU (3)· patent assignee history
2012–2021Based in Zhubei City, TW· patent location history
2015–2020Based in Hsinchu County, TW· patent location history
2016–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (24)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 24 | 2016–2021 |
| TAIWAN SEMICONDUCTOR MFG | 19 | 2005–2016 |
| KUAN JUI-FENGself | 6 | 2012–2014 |
| CHENG YI-KAN | 5 | 2012–2013 |
| CHAO HSIAO-SHU | 3 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Zhubei City, TW | 38 | 2012–2021 |
| Hsinchu County, TW | 4 | 2015–2020 |
| Hsinchu, TW | 1 | 2005 |