Inventor
Ming-Shih Yeh
Inventor
Jhubei City, TW
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1039%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1029%
H01LSemiconductor devices25%
H10DInorganic electric semiconductor devices4%
H10HInorganic light-emitting semiconductor devices having potential barriers1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
10,879,224Package structure, die and method of manufacturing the same202010,872,855Chip package and method of fabricating the same202010,867,928Semiconductor device and manufacturing method thereof202010,784,207Multi-stacked package-on-package structures202010,756,037Package structure and fabricating method thereof202010,636,775Package structure and manufacturing method thereof202010,629,477Raised via for terminal connections on different planes202010,622,302Via for semiconductor device connection and methods of forming the same202010,529,650Semiconductor package and method202010,461,036Multi-stacked package-on-package structures201910,319,683Multi-stacked package-on-package structures201910,297,494Raised via for terminal connections on different planes201910,290,610PoP device and method of forming the same201910,163,803Integrated fan-out packages and methods of forming the same201810,157,852Multi-stacked package-on-package structures20189,224,643'Structure and method for tunable interconnect scheme'20158,987,085'Methods for improving uniformity of cap layers'20158,623,760'Process for improving copper line cap formation'20148,432,040'Interconnection structure design for low RC delay and leakage'20138,193,087'Process for improving copper line cap formation'20128,109,407'Apparatus for storing substrates'20128,106,512'Low resistance high reliability contact via and metal line structure for semiconductor device'20128,053,865'MOM capacitors integrated with air-gaps'20118,013,445'Low resistance high reliability contact via and metal line structure for semiconductor device'20117,651,943'Forming diffusion barriers by annealing copper alloy layers'20107,354,856'Method for forming dual damascene structures with tapered via portions and improved performance'20087,179,732'Interconnection structure and fabrication method thereof'20076,890,851'Interconnection structure and fabrication method thereof'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2007Based in Changhua County, TW· patent location history
2008–2015Patents assigned to TAIWAN SEMICONDUCTOR MFG (10)· patent assignee history
2008–2020Based in Hsinchu, TW· patent location history
2010–2015Based in Jhubei City, TW· patent location history
2012–2015Patents assigned to YEH MING-SHIH (7)· patent assignee history
2012–2015Patents assigned to YU CHEN-HUA (6)· patent assignee history
2012–2014Patents assigned to SHIH CHIEN-HSUEH (2)· patent assignee history
2018–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (15)· patent assignee history
2018–2020Based in Hsinchu County, TW· patent location history
2018–2020Based in Zhubei City, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 15 | 2018–2020 |
| TAIWAN SEMICONDUCTOR MFG | 10 | 2008–2015 |
| YEH MING-SHIHself | 7 | 2012–2015 |
| YU CHEN-HUA | 6 | 2012–2015 |
| SHIH CHIEN-HSUEH | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Jhubei City, TW | 9 | 2010–2015 |
| Hsinchu County, TW | 6 | 2018–2020 |
| Zhubei City, TW | 6 | 2018–2020 |
| Hsinchu, TW | 4 | 2008–2020 |
| Changhua County, TW | 2 | 2005–2007 |