Inventor
Paul A. Clifton
Inventor
Redwood City, CA, US
Overview
Patents· 44 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices27%
H01LSemiconductor devices18%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
B82YSpecific uses or applications of nanostructures7%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light4%
H10HInorganic light-emitting semiconductor devices having potential barriers4%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution4%
H04LTransmission of digital information, e.g. telegraphic communication3%
PatentTitleYear
10,950,727Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer202110,879,366Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers202010,872,964MIS contact structure with metal oxide conductor202010,833,194SOI wafers and devices with buried stressor202010,833,199Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height202010,727,647Tensile strained semiconductor photon emission and detection devices and integrated photonics system202010,580,896Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer202010,553,695MIS contact structure with metal oxide conductor202010,505,005Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers201910,505,047Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height201910,193,307Tensile strained semiconductor photon emission and detection devices and integrated photonics system201910,170,627Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height201910,147,798MIS contact structure with metal oxide conductor201810,084,091Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer201810,008,827Tensile strained semiconductor photon emission and detection devices and integrated photonics system20189,755,038'Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers'20179,673,327'Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer'20179,620,611'MIS contact structure with metal oxide conductor'20179,484,426'Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers'20169,406,798'Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer'20169,362,376'Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers'20169,270,083'Tensile strained semiconductor photon emission and detection devices and integrated photonics system'20169,059,201'Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation'20159,036,672'Tensile strained semiconductor photon emission and detection devices and integrated photonics system'20159,029,686'Strain-enhanced silicon photon-to-electron conversion devices'20158,731,017'Tensile strained semiconductor photon emission and detection devices and integrated photonics system'20148,658,523'Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)'20148,450,133'Strained-enhanced silicon photon-to-electron conversion devices'20138,395,213'Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer'20138,361,868'Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation'20138,361,867'Biaxial strained field effect transistor devices'20138,263,466'Channel strain induced by strained metal in FET source or drain'20128,263,467'Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor'20128,212,336'Field effect transistor source or drain with a multi-facet surface'20128,003,486'Method of making a semiconductor device having a strained semiconductor active region using edge relaxation, a buried stressor layer and a sacrificial stressor layer'20117,977,147'Strained silicon with elastic edge relaxation'20117,972,916'Method of forming a field effect transistors with a sacrificial stressor layer and strained source and drain regions formed in recesses'20117,902,029'Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor'20117,851,325'Strained semiconductor using elastic edge relaxation, a buried stressor layer and a sacrificial stressor layer'20107,816,240'Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)'20107,700,416'Tensile strained semiconductor on insulator using elastic edge relaxation and a sacrificial stressor layer'20107,612,365'Strained silicon with elastic edge relaxation'20097,338,834'Strained silicon with elastic edge relaxation'20086,847,063'Semiconductor device'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2012Based in Menlo Park, CA, US· patent location history
2008–2020Patents assigned to ACORN TECH INC (38)· patent assignee history
2008–2014Based in Mountain View, CA, US· patent location history
2011Based in Pacific Palisades, CA, US· patent location history
2012–2016Patents assigned to CLIFTON PAUL A (10)· patent assignee history
2012–2014Patents assigned to CONNELLY DANIEL J (4)· patent assignee history
2013–2016Patents assigned to GAINES R STOCKTON (3)· patent assignee history
2014–2021Based in Redwood City, CA, US· patent location history
2016–2020Based in Palo Alto, CA, US· patent location history
2019–2021Patents assigned to ACORN SEMI LLC (10)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ACORN TECH INC | 38 | 2008–2020 |
| ACORN SEMI LLC | 10 | 2019–2021 |
| CLIFTON PAUL Aself | 10 | 2012–2016 |
| CONNELLY DANIEL J | 4 | 2012–2014 |
| GAINES R STOCKTON | 3 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Redwood City, California, US | 17 | 2014–2021 |
| Mountain View, California, US | 13 | 2008–2014 |
| Palo Alto, California, US | 9 | 2016–2020 |
| Menlo Park, California, US | 4 | 2005–2012 |
| Pacific Palisades, California, US | 1 | 2011 |