Inventor
Chiarn-Lung Lee
Inventor
Hsinchu, TW
Overview
Patents· 6 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1055%
C23CCoating metallic material18%
H10DInorganic electric semiconductor devices9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
PatentTitleYear
6,440,859'Method for etching passivation layer of wafer'20026,294,483'Method for preventing delamination of APCVD BPSG films'20016,245,688'Dry Air/N2 post treatment to avoid the formation of B/P precipitation after BPSG film deposition'20016,090,675'Formation of dielectric layer employing high ozone:tetraethyl-ortho-silicate ratios during chemical vapor deposition'20005,935,876'Via structure using a composite dielectric layer'19995,865,900'Etch method for removing metal-fluoropolymer residues'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2002Patents assigned to TAIWAN SEMICONDUCTOR MFG (6)· patent assignee history
1999–2002Based in Hsinchu, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 6 | 1999–2002 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 6 | 1999–2002 |