Inventor
John Michael Hergenrother
Inventor
Ridgefield, CT, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices39%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation8%
B82YSpecific uses or applications of nanostructures6%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices6%
H01JElectric discharge tubes or discharge lamps6%
H10BElectronic memory devices2%
PatentTitleYear
8,120,138'High-Z structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels'20127,943,486'Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain'20117,859,061'Halo-first ultra-thin SOI FET for superior short channel control'20107,696,057'Method for co-alignment of mixed optical and electron beam lithographic fabrication levels'20107,687,863'Selective incorporation of charge for transistor channels'20107,595,247'Halo-first ultra-thin SOI FET for superior short channel control'20097,550,361'Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels'20097,462,525'Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain'20087,374,998'Selective incorporation of charge for transistor channels'20087,314,790'Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain'20087,161,169'Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain'20076,903,411'Architecture for circuit connection of a vertical transistor'20056,828,628'Diffused MOS devices with strained silicon portions and methods for forming same'20046,821,851'Method of making ultra thin body vertical replacement gate MOSFET'20046,653,181'CMOS integrated circuit having vertical transistors and a process for fabricating same'20036,635,924'Ultra thin body vertical replacement gate MOSFET'20036,518,622'Vertical replacement gate (VRG) MOSFET with a conductive layer adjacent a source/drain region and method of manufacture therefor'20036,197,641'Process for fabricating vertical transistors'20016,027,975'Process for fabricating vertical transistors'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2001Patents assigned to LUCENT TECHNOLOGIES INC (2)· patent assignee history
2000–2005Based in Short Hills, NJ, US· patent location history
2003–2005Patents assigned to AGERE SYSTEMS INC (6)· patent assignee history
2003Based in Shorthills, NJ, US· patent location history
2007–2012Patents assigned to IBM (11)· patent assignee history
2007–2012Based in Ridgefield, CT, US· patent location history
2012Patents assigned to FRIED DAVID MICHAEL (1)· patent assignee history
2012Patents assigned to HERGENROTHER JOHN MICHAEL (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 11 | 2007–2012 |
| AGERE SYSTEMS INC | 6 | 2003–2005 |
| LUCENT TECHNOLOGIES INC | 2 | 2000–2001 |
| FRIED DAVID MICHAEL | 1 | 2012 |
| HERGENROTHER JOHN MICHAELself | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Ridgefield, CT, US | 11 | 2007–2012 |
| Short Hills, New Jersey, US | 7 | 2000–2005 |
| Shorthills, New Jersey, US | 1 | 2003 |