Inventor
Sungryul Kim
Inventor
San Diego, CA, US
Overview
Patents· 50 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores29%
G06FElectric digital data processing17%
H01LSemiconductor devices9%
H10NElectric solid-state devices not otherwise provided for5%
G09GArrangements or circuits for control of indicating devices using static means to present variable information4%
H04LTransmission of digital information, e.g. telegraphic communication4%
H10BElectronic memory devices4%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein4%
H03MCoding4%
H04WWireless communication networks4%
PatentTitleYear
11,132,087Display device202110,803,942Transistor noise tolerant, non-volatile (NV) resistance element-based static random access memory (SRAM) physically unclonable function (PUF) circuits, and related systems and methods202010,740,017Dynamic memory protection202010,715,374Long range (LoRa) communication system and method with improved data rate202010,636,962Spin-orbit torque (SOT) magnetic tunnel junction (MTJ) (SOT-MTJ) devices employing perpendicular and in-plane free layer magnetic anisotropy to facilitate perpendicular magnetic orientation switching, suitable for use in memory systems for storing data202010,530,628Long range (LoRa) communication system and method with improved data rate202010,492,106Adaptive data rate control method and adaptive data rate control system201910,460,780Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory201910,381,060High-speed, low power spin-orbit torque (SOT) assisted spin-transfer torque magnetic random access memory (STT-MRAM) bit cell array201910,340,297Display device201910,319,425Offset-cancellation sensing circuit (OCSC)-based non-volatile (NV) memory circuits201910,311,930One-time programming (OTP) magneto-resistive random access memory (MRAM) bit cells in a physically unclonable function (PUF) memory in breakdown to a memory state from a previous read operation to provide PUF operations201910,290,340Offset-canceling (OC) write operation sensing circuits for sensing switching in a magneto-resistive random access memory (MRAM) bit cell in an MRAM for a write operation201910,263,645Error correction and decoding201910,249,814Dynamic memory protection201910,224,087Sensing voltage based on a supply voltage applied to magneto-resistive random access memory (MRAM) bit cells in an MRAM for tracking write operations to the MRAM bit cells201910,133,114Display device having a light blocking pattern201810,115,444Data bit inversion tracking in cache memory to reduce data bits written for write operations20189,800,271'Error correction and decoding'20179,753,874'Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems'20179,672,885'MRAM word line power control scheme'20179,653,183'Shared built-in self-analysis of memory systems employing a memory array tile architecture'20179,633,706'Voltage self-boosting circuit for generating a boosted voltage for driving a word line write in a memory array for a memory write operation'20179,612,908'Performing memory data scrubbing operations in processor-based memory in response to periodic memory controller wake-up periods'20179,583,170'Adjusting resistive memory write driver strength based on a mimic resistive memory write operation'20179,583,171'Write driver circuits for resistive random access memory (RAM) arrays'20179,552,244'Real time correction of bit failure in resistive memory'20179,495,261'Systems and methods for reducing memory failures'20169,455,014'Adjusting resistive memory write driver strength based on write error rate (WER) to improve WER yield, and related methods and systems'20169,455,013'System and method to trim reference levels in a resistive memory'20169,431,129'Variable read delay system'20169,401,226'MRAM initialization devices and methods'20169,336,847'Method and apparatus for generating a reference for use with a magnetic tunnel junction'20169,275,714'Read operation of MRAM using a dummy word line'20169,262,263'Bit recovery system'20169,261,999'Display panel having embedded light sensors'20169,251,881'System and method to trim reference levels in a resistive memory'20169,183,082'Error detection and correction of one-time programmable elements'20159,165,631'OTP scheme with multiple magnetic tunnel junction devices in a cell'20159,153,307'System and method to provide a reference cell'20159,147,457'Reference cell repair scheme'20159,140,747'Sense amplifier offset voltage reduction'20159,135,975'Write pulse width scheme in a resistive memory'20159,030,460'Display apparatus'20159,029,971'Display apparatus and method of manufacturing touch substrate'20158,976,305'Display apparatus and method of manufacturing the same'20158,923,044'MTP MTJ device'20148,913,450'Memory cell array with reserved sector for storing configuration information'20148,717,336'Light sensing panel and display apparatus having the same'20148,698,167'Light sensor and display apparatus having the same'2014Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2014–2020Patents assigned to QUALCOMM INC (36)· patent assignee history
2014–2017Patents assigned to KIM SUNGRYUL (9)· patent assignee history
2014–2021Patents assigned to SAMSUNG DISPLAY CO LTD (9)· patent assignee history
2014–2016Patents assigned to BANG JUNG SUK (5)· patent assignee history
2014–2016Patents assigned to CHO BYEONGHOON (5)· patent assignee history
2014–2020Based in San Diego, CA, US· patent location history
2014–2019Based in Asan-si, KR· patent location history
2019–2020Based in Yangsan-si, KR· patent location history
2021Based in Seongnam-si, KR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QUALCOMM INC | 36 | 2014–2020 |
| KIM SUNGRYULself | 9 | 2014–2017 |
| SAMSUNG DISPLAY CO LTD | 9 | 2014–2021 |
| BANG JUNG SUK | 5 | 2014–2016 |
| CHO BYEONGHOON | 5 | 2014–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Diego, California, US | 38 | 2014–2020 |
| Asan-si, KR | 8 | 2014–2019 |
| Yangsan-si, KR | 3 | 2019–2020 |
| Seongnam-si, KR | 1 | 2021 |